From patchwork Thu Nov 20 21:24:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 5350841 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A885A9F1E1 for ; Thu, 20 Nov 2014 21:24:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF7E2201E4 for ; Thu, 20 Nov 2014 21:24:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 24280201ED for ; Thu, 20 Nov 2014 21:24:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DBE26F650; Thu, 20 Nov 2014 13:24:32 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pd0-f174.google.com (mail-pd0-f174.google.com [209.85.192.174]) by gabe.freedesktop.org (Postfix) with ESMTP id 690B66F650 for ; Thu, 20 Nov 2014 13:24:30 -0800 (PST) Received: by mail-pd0-f174.google.com with SMTP id w10so3792165pde.5 for ; Thu, 20 Nov 2014 13:24:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:subject:date:message-id:in-reply-to:references; bh=7JSlvWlW4VO49ZCeHGjoU6c6PqCT/1nUuIj+nwkT2vY=; b=Ngs8GyHvoPVeqNsk/gUvh41KJlQlPYP/aBDrIWfrRnLa9o58/n53EleuKABmfmUSR9 Nb+uacADUH8l5wyP8iuoDR8Fh26nFqLL6QIZrvIlwUEqnTFSCsmXkKrPpwMdhsYxEV2M rf+54L9q+GZGPwxy3N4lSfUB1IGBWzxpXv3iCDYL8rCGq+alos3a+rcE0lFkOLXIE3kb oIAgRZNYvGSTDdzARwrJGdG7Jf3uRwMFPf0dIiBgIS6DgKqKNMwyRPmKbNxFpBpkPwFY Gy2zMhfnEF4EcFLT4aSvEYHFc7ILhjIXW4opUSYfN7PwHEfyuPMZGdOBRZwK2RmffZKU XneA== X-Received: by 10.68.57.200 with SMTP id k8mr880335pbq.96.1416518670267; Thu, 20 Nov 2014 13:24:30 -0800 (PST) Received: from jbarnes-t420.intel.com (c-67-161-37-189.hsd1.ca.comcast.net. [67.161.37.189]) by mx.google.com with ESMTPSA id pe6sm2900349pac.21.2014.11.20.13.24.29 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Nov 2014 13:24:29 -0800 (PST) From: Jesse Barnes To: intel-gfx@lists.freedesktop.org Date: Thu, 20 Nov 2014 13:24:14 -0800 Message-Id: <1416518654-28749-2-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1416518654-28749-1-git-send-email-jbarnes@virtuousgeek.org> References: <1416518654-28749-1-git-send-email-jbarnes@virtuousgeek.org> Subject: [Intel-gfx] [PATCH 2/2] drm/i915/ibx: check port in infoframe_enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Just like on g4x we need to check the port enable bit here. Signed-off-by: Jesse Barnes Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/intel_hdmi.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index ec87333..cc48b51 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -222,10 +222,15 @@ static bool ibx_infoframe_enabled(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); u32 val = I915_READ(reg); + u32 port = VIDEO_DIP_PORT(intel_dig_port->port); - return val & VIDEO_DIP_ENABLE; + if (port == (val & VIDEO_DIP_PORT_MASK)) + return val & VIDEO_DIP_ENABLE; + + return false; } static void cpt_write_infoframe(struct drm_encoder *encoder,