From patchwork Mon Dec 1 06:58:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 5410191 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3C349BEEA8 for ; Mon, 1 Dec 2014 06:57:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 458BF20274 for ; Mon, 1 Dec 2014 06:57:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3FC7B2010B for ; Mon, 1 Dec 2014 06:57:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B2A616E10F; Sun, 30 Nov 2014 22:57:19 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id ED1946E100 for ; Sun, 30 Nov 2014 22:57:17 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 30 Nov 2014 22:54:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,491,1413270000"; d="scan'208";a="646033073" Received: from sagar-desktop.iind.intel.com ([10.223.82.56]) by orsmga002.jf.intel.com with ESMTP; 30 Nov 2014 22:57:15 -0800 From: sagar.a.kamble@intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 1 Dec 2014 12:28:04 +0530 Message-Id: <1417417085-32419-1-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.8.5 Cc: Akash Goel , Sagar Kamble Subject: [Intel-gfx] [PATCH v1 1/2] drm/i915: Enabling RC6 immediately instead of enabling via delayed work item X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sagar Kamble RC6 was getting enabled through deferred work item which was scheduled after 1s. This will keep render and media well ON for 1s. Since RC6 enabling does not involve PCU communication, processing time in intel_enable_gt_powersave will not be increased. Enabling RC6 immediately will help power gate render and media well immediately that will save power. Signed-off-by: Akash Goel Signed-off-by: Sagar Kamble --- drivers/gpu/drm/i915/intel_pm.c | 88 ++++++++++++++++++++++++++++------------- 1 file changed, 61 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9af0af4..1fb3084 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5276,11 +5276,11 @@ static void valleyview_cleanup_gt_powersave(struct drm_device *dev) valleyview_cleanup_pctx(dev); } -static void cherryview_enable_rps(struct drm_device *dev) +static void cherryview_enable_rc6(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *ring; - u32 gtfifodbg, val, rc6_mode = 0, pcbr; + u32 gtfifodbg, rc6_mode = 0, pcbr; int i; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -5294,10 +5294,10 @@ static void cherryview_enable_rps(struct drm_device *dev) cherryview_check_pctx(dev_priv); - /* 1a & 1b: Get forcewake during program sequence. Although the driver - * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); - + /* + * Assuming RC6 disabled by uncore_sanitize we dont need to do + * force wake get/put here. + */ /* 2a: Program RC6 thresholds.*/ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ @@ -5324,6 +5324,18 @@ static void cherryview_enable_rps(struct drm_device *dev) rc6_mode = GEN6_RC_CTL_EI_MODE(1); I915_WRITE(GEN6_RC_CONTROL, rc6_mode); +} + +static void cherryview_enable_rps(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 val; + + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); + + /* 1a & 1b: Get forcewake during program sequence. Although the driver + * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ + gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); /* 4 Program defaults and thresholds for RPS*/ I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); @@ -5367,11 +5379,11 @@ static void cherryview_enable_rps(struct drm_device *dev) gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); } -static void valleyview_enable_rps(struct drm_device *dev) +static void valleyview_enable_rc6(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *ring; - u32 gtfifodbg, val, rc6_mode = 0; + u32 gtfifodbg, rc6_mode = 0; int i; WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); @@ -5384,25 +5396,10 @@ static void valleyview_enable_rps(struct drm_device *dev) I915_WRITE(GTFIFODBG, gtfifodbg); } - /* If VLV, Forcewake all wells, else re-direct to regular path */ - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); - - I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); - I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); - I915_WRITE(GEN6_RP_UP_EI, 66000); - I915_WRITE(GEN6_RP_DOWN_EI, 350000); - - I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); - I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); - - I915_WRITE(GEN6_RP_CONTROL, - GEN6_RP_MEDIA_TURBO | - GEN6_RP_MEDIA_HW_NORMAL_MODE | - GEN6_RP_MEDIA_IS_GFX | - GEN6_RP_ENABLE | - GEN6_RP_UP_BUSY_AVG | - GEN6_RP_DOWN_IDLE_CONT); - + /* + * Assuming RC6 disabled by uncore_sanitize we dont need to do + * force wake get/put here. + */ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); @@ -5425,6 +5422,32 @@ static void valleyview_enable_rps(struct drm_device *dev) intel_print_rc6_info(dev, rc6_mode); I915_WRITE(GEN6_RC_CONTROL, rc6_mode); +} + +static void valleyview_enable_rps(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 val; + + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); + + gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + + I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); + I915_WRITE(GEN6_RP_UP_EI, 66000); + I915_WRITE(GEN6_RP_DOWN_EI, 350000); + + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); + + I915_WRITE(GEN6_RP_CONTROL, + GEN6_RP_MEDIA_TURBO | + GEN6_RP_MEDIA_HW_NORMAL_MODE | + GEN6_RP_MEDIA_IS_GFX | + GEN6_RP_ENABLE | + GEN6_RP_UP_BUSY_AVG | + GEN6_RP_DOWN_IDLE_CONT); val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); @@ -6295,6 +6318,17 @@ void intel_enable_gt_powersave(struct drm_device *dev) mutex_unlock(&dev->struct_mutex); } else if (INTEL_INFO(dev)->gen >= 6) { /* + * Enabling RC6 for VLV & CHV here itself and only deferring turbo + * enabling. + */ + mutex_lock(&dev_priv->rps.hw_lock); + if (IS_CHERRYVIEW(dev)) + cherryview_enable_rc6(dev); + else if (IS_VALLEYVIEW(dev)) + valleyview_enable_rc6(dev); + mutex_unlock(&dev_priv->rps.hw_lock); + + /* * PCU communication is slow and this doesn't need to be * done at any specific time, so do this out of our fast path * to make resume and init faster.