From patchwork Wed Dec 3 19:15:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 5433451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 744C59F319 for ; Wed, 3 Dec 2014 20:55:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9ACA1202B8 for ; Wed, 3 Dec 2014 20:55:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 939DC20225 for ; Wed, 3 Dec 2014 20:55:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24DE26E554; Wed, 3 Dec 2014 12:55:01 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DF7A6E554 for ; Wed, 3 Dec 2014 12:55:00 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 03 Dec 2014 11:15:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,509,1413270000"; d="scan'208";a="618087563" Received: from asiluver-linux.isw.intel.com ([10.102.226.168]) by orsmga001.jf.intel.com with ESMTP; 03 Dec 2014 11:15:40 -0800 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Wed, 3 Dec 2014 19:15:31 +0000 Message-Id: <1417634131-9573-1-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 2.1.2 Subject: [Intel-gfx] [PATCH] drm/i915/chv: Add additional workarounds for CHV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP These w/a were recently identified while debugging another issue, +WaClearFlowControlGpgpuContextSave:chv +Wa4x4STCOptimizationDisable:chv For: VIZ-4090 Change-Id: I08d2176dec609396c3a7c2e48b2413e233799fc4 Signed-off-by: Arun Siluvery Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dc03fac..7c7663f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6131,6 +6131,7 @@ enum punit_power_well { #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) #define GEN8_ROW_CHICKEN 0xe4f0 +#define FLOW_CONTROL_ENABLE (1<<15) #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) #define STALL_DOP_GATING_DISABLE (1<<5) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 79b4ca5..525c9bf 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -796,8 +796,10 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) /* WaDisablePartialInstShootdown:chv */ /* WaDisableThreadStallDopClockGating:chv */ + /* WaClearFlowControlGpgpuContextSave:chv */ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | + FLOW_CONTROL_ENABLE | STALL_DOP_GATING_DISABLE); /* Use Force Non-Coherent whenever executing a 3D context. This is a @@ -810,6 +812,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) HDC_FORCE_NON_COHERENT | HDC_DONOT_FETCH_MEM_WHEN_MASKED); + /* Wa4x4STCOptimizationDisable:chv */ + WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); + return 0; }