| Message ID | 1417707632-8656-1-git-send-email-michel.thierry@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 364/364 364/364
ILK 366/366 366/366
SNB 450/450 450/450
IVB +17 481/498 498/498
BYT 289/289 289/289
HSW 564/564 564/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
IVB igt_kms_3d DMESG_WARN(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-128x128-onscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-128x128-random NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-128x128-sliding NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-256x256-offscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-256x256-onscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-256x256-sliding NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-64x64-offscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-64x64-onscreen NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-64x64-random NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-64x64-sliding NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_cursor_crc_cursor-size-change NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_fence_pin_leak NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_rotation_crc_primary-rotation NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
IVB igt_kms_rotation_crc_sprite-rotation NSPT(1, M34)PASS(8, M4M34M21) PASS(1, M4)
Note: You need to pay more attention to line start with '*'
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 788e1b6..5b51a43 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -756,9 +756,12 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) * workaround for for a possible hang in the unlikely event a TLB * invalidation occurs during a PSD flush. */ + /* WaForceEnableNonCoherent:bdw */ + /* WaHdcDisableFetchWhenMasked:bdw */ /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */ WA_SET_BIT_MASKED(HDC_CHICKEN0, HDC_FORCE_NON_COHERENT | + HDC_DONOT_FETCH_MEM_WHEN_MASKED | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); /* Wa4x4STCOptimizationDisable:bdw */
We already have it for chv, but was missing for bdw. v2: Label WaForceEnableNonCoherent (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 1 file changed, 3 insertions(+)