[RFC,3/8] drm/i915: Pass new_config down do crtc_compute_clock

Commit Message

Ander Conselvan de Oliveira Dec. 8, 2014, 3:21 p.m. UTC

This reduces the number of direct users of crtc->new_config. At some
point we'll be able to get rid of that pointer altogether, in favor
of drm core state structs.
---
 drivers/gpu/drm/i915/i915_drv.h      |   3 +-
 drivers/gpu/drm/i915/intel_ddi.c     |  29 ++++----
 drivers/gpu/drm/i915/intel_display.c | 131 +++++++++++++++++++----------------
 drivers/gpu/drm/i915/intel_drv.h     |   6 +-
 4 files changed, 94 insertions(+), 75 deletions(-)

Comments

Daniel Vetter Dec. 8, 2014, 4:32 p.m. UTC | #1

On Mon, Dec 08, 2014 at 05:21:04PM +0200, Ander Conselvan de Oliveira wrote:
> This reduces the number of direct users of crtc->new_config. At some
> point we'll be able to get rid of that pointer altogether, in favor
> of drm core state structs.

Just an aside: If we want to use drm_obj->state instead of new_config then
we deviate a bit from the helpers: The helpers only apply the new state to
state pointers in ->commit, we have our ->new_config pointer already set
in the compute/check config phase. Essentially it's not the same thing.

Now with the drm core you can just look up any state object you need, but
that'll lead to a bit more cumbersome code maybe. Otoh if we keep using
->new_config we need those in our ->atomic_check and then reapply in
->atomic_commit.

I'm ok with either approach really, so will leave it to you.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |   3 +-
>  drivers/gpu/drm/i915/intel_ddi.c     |  29 ++++----
>  drivers/gpu/drm/i915/intel_display.c | 131 +++++++++++++++++++----------------
>  drivers/gpu/drm/i915/intel_drv.h     |   6 +-
>  4 files changed, 94 insertions(+), 75 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7d60d38..c1a9af9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -500,7 +500,8 @@ struct drm_i915_display_funcs {
>  				struct intel_crtc_state *);
>  	void (*get_plane_config)(struct intel_crtc *,
>  				 struct intel_plane_config *);
> -	int (*crtc_compute_clock)(struct intel_crtc *crtc);
> +	int (*crtc_compute_clock)(struct intel_crtc *crtc,
> +				  struct intel_crtc_state *crtc_state);
>  	void (*crtc_enable)(struct drm_crtc *crtc);
>  	void (*crtc_disable)(struct drm_crtc *crtc);
>  	void (*off)(struct drm_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 79c9776..970ca30 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -904,6 +904,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
>  
>  static bool
>  hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
> +		   struct intel_crtc_state *crtc_state,
>  		   struct intel_encoder *intel_encoder,
>  		   int clock)
>  {
> @@ -918,16 +919,16 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
>  		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
>  		      WRPLL_DIVIDER_POST(p);
>  
> -		intel_crtc->new_config->dpll_hw_state.wrpll = val;
> +		crtc_state->dpll_hw_state.wrpll = val;
>  
> -		pll = intel_get_shared_dpll(intel_crtc);
> +		pll = intel_get_shared_dpll(intel_crtc, crtc_state);
>  		if (pll == NULL) {
>  			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
>  					 pipe_name(intel_crtc->pipe));
>  			return false;
>  		}
>  
> -		intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
> +		crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
>  	}
>  
>  	return true;
> @@ -1090,6 +1091,7 @@ found:
>  
>  static bool
>  skl_ddi_pll_select(struct intel_crtc *intel_crtc,
> +		   struct intel_crtc_state *crtc_state,
>  		   struct intel_encoder *intel_encoder,
>  		   int clock)
>  {
> @@ -1139,11 +1141,11 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  	} else /* eDP */
>  		return true;
>  
> -	intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
> -	intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
> -	intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;
> +	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
> +	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
> +	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
>  
> -	pll = intel_get_shared_dpll(intel_crtc);
> +	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
>  	if (pll == NULL) {
>  		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
>  				 pipe_name(intel_crtc->pipe));
> @@ -1151,7 +1153,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>  	}
>  
>  	/* shared DPLL id 0 is DPLL 1 */
> -	intel_crtc->new_config->ddi_pll_sel = pll->id + 1;
> +	crtc_state->ddi_pll_sel = pll->id + 1;
>  
>  	return true;
>  }
> @@ -1163,17 +1165,20 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>   * For private DPLLs, compute_config() should do the selection for us. This
>   * function should be folded into compute_config() eventually.
>   */
> -bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
> +bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
> +			  struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_device *dev = intel_crtc->base.dev;
>  	struct intel_encoder *intel_encoder =
>  		intel_ddi_get_crtc_new_encoder(intel_crtc);
> -	int clock = intel_crtc->new_config->port_clock;
> +	int clock = crtc_state->port_clock;
>  
>  	if (IS_SKYLAKE(dev))
> -		return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
> +		return skl_ddi_pll_select(intel_crtc, crtc_state,
> +					  intel_encoder, clock);
>  	else
> -		return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
> +		return hsw_ddi_pll_select(intel_crtc, crtc_state,
> +					  intel_encoder, clock);
>  }
>  
>  void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f836f67..3bceacb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3858,7 +3858,8 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
>  	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
>  }
>  
> -struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
> +struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
> +						struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
>  	struct intel_shared_dpll *pll;
> @@ -3884,7 +3885,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
>  		if (pll->new_config->crtc_mask == 0)
>  			continue;
>  
> -		if (memcmp(&crtc->new_config->dpll_hw_state,
> +		if (memcmp(&crtc_state->dpll_hw_state,
>  			   &pll->new_config->hw_state,
>  			   sizeof(pll->new_config->hw_state)) == 0) {
>  			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
> @@ -3909,9 +3910,9 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
>  
>  found:
>  	if (pll->new_config->crtc_mask == 0)
> -		pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
> +		pll->new_config->hw_state = crtc_state->dpll_hw_state;
>  
> -	crtc->new_config->shared_dpll = i;
> +	crtc_state->shared_dpll = i;
>  	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
>  			 pipe_name(crtc->pipe));
>  
> @@ -5726,30 +5727,31 @@ static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
>  }
>  
>  static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
> +				     struct intel_crtc_state *crtc_state,
>  				     intel_clock_t *reduced_clock)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	u32 fp, fp2 = 0;
>  
>  	if (IS_PINEVIEW(dev)) {
> -		fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
> +		fp = pnv_dpll_compute_fp(&crtc_state->dpll);
>  		if (reduced_clock)
>  			fp2 = pnv_dpll_compute_fp(reduced_clock);
>  	} else {
> -		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
> +		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
>  		if (reduced_clock)
>  			fp2 = i9xx_dpll_compute_fp(reduced_clock);
>  	}
>  
> -	crtc->new_config->dpll_hw_state.fp0 = fp;
> +	crtc_state->dpll_hw_state.fp0 = fp;
>  
>  	crtc->lowfreq_avail = false;
>  	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
>  	    reduced_clock && i915.powersave) {
> -		crtc->new_config->dpll_hw_state.fp1 = fp2;
> +		crtc_state->dpll_hw_state.fp1 = fp2;
>  		crtc->lowfreq_avail = true;
>  	} else {
> -		crtc->new_config->dpll_hw_state.fp1 = fp;
> +		crtc_state->dpll_hw_state.fp1 = fp;
>  	}
>  }
>  
> @@ -6084,6 +6086,7 @@ void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
>  }
>  
>  static void i9xx_update_pll(struct intel_crtc *crtc,
> +			    struct intel_crtc_state *crtc_state,
>  			    intel_clock_t *reduced_clock,
>  			    int num_connectors)
>  {
> @@ -6091,9 +6094,9 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 dpll;
>  	bool is_sdvo;
> -	struct dpll *clock = &crtc->new_config->dpll;
> +	struct dpll *clock = &crtc_state->dpll;
>  
> -	i9xx_update_pll_dividers(crtc, reduced_clock);
> +	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
>  
>  	is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
>  		intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
> @@ -6106,14 +6109,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
>  		dpll |= DPLLB_MODE_DAC_SERIAL;
>  
>  	if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
> -		dpll |= (crtc->new_config->pixel_multiplier - 1)
> +		dpll |= (crtc_state->pixel_multiplier - 1)
>  			<< SDVO_MULTIPLIER_SHIFT_HIRES;
>  	}
>  
>  	if (is_sdvo)
>  		dpll |= DPLL_SDVO_HIGH_SPEED;
>  
> -	if (crtc->new_config->has_dp_encoder)
> +	if (crtc_state->has_dp_encoder)
>  		dpll |= DPLL_SDVO_HIGH_SPEED;
>  
>  	/* compute bitmask from p1 value */
> @@ -6141,7 +6144,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
>  	if (INTEL_INFO(dev)->gen >= 4)
>  		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
>  
> -	if (crtc->new_config->sdvo_tv_clock)
> +	if (crtc_state->sdvo_tv_clock)
>  		dpll |= PLL_REF_INPUT_TVCLKINBC;
>  	else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
>  		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> @@ -6150,25 +6153,26 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
>  		dpll |= PLL_REF_INPUT_DREFCLK;
>  
>  	dpll |= DPLL_VCO_ENABLE;
> -	crtc->new_config->dpll_hw_state.dpll = dpll;
> +	crtc_state->dpll_hw_state.dpll = dpll;
>  
>  	if (INTEL_INFO(dev)->gen >= 4) {
> -		u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
> +		u32 dpll_md = (crtc_state->pixel_multiplier - 1)
>  			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
> -		crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
> +		crtc_state->dpll_hw_state.dpll_md = dpll_md;
>  	}
>  }
>  
>  static void i8xx_update_pll(struct intel_crtc *crtc,
> +			    struct intel_crtc_state *crtc_state,
>  			    intel_clock_t *reduced_clock,
>  			    int num_connectors)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	u32 dpll;
> -	struct dpll *clock = &crtc->new_config->dpll;
> +	struct dpll *clock = &crtc_state->dpll;
>  
> -	i9xx_update_pll_dividers(crtc, reduced_clock);
> +	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
>  
>  	dpll = DPLL_VGA_MODE_DIS;
>  
> @@ -6193,7 +6197,7 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
>  		dpll |= PLL_REF_INPUT_DREFCLK;
>  
>  	dpll |= DPLL_VCO_ENABLE;
> -	crtc->new_config->dpll_hw_state.dpll = dpll;
> +	crtc_state->dpll_hw_state.dpll = dpll;
>  }
>  
>  static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
> @@ -6389,7 +6393,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
>  	POSTING_READ(PIPECONF(intel_crtc->pipe));
>  }
>  
> -static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
> +static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
> +				   struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -6421,7 +6426,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
>  	if (is_dsi)
>  		return 0;
>  
> -	if (!crtc->new_config->clock_set) {
> +	if (!crtc_state->clock_set) {
>  		refclk = i9xx_get_refclk(crtc, num_connectors);
>  
>  		/*
> @@ -6432,7 +6437,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
>  		 */
>  		limit = intel_limit(crtc, refclk);
>  		ok = dev_priv->display.find_dpll(limit, crtc,
> -						 crtc->new_config->port_clock,
> +						 crtc_state->port_clock,
>  						 refclk, NULL, &clock);
>  		if (!ok) {
>  			DRM_ERROR("Couldn't find PLL settings for mode!\n");
> @@ -6453,23 +6458,23 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
>  							    &reduced_clock);
>  		}
>  		/* Compat-code for transition, will disappear. */
> -		crtc->new_config->dpll.n = clock.n;
> -		crtc->new_config->dpll.m1 = clock.m1;
> -		crtc->new_config->dpll.m2 = clock.m2;
> -		crtc->new_config->dpll.p1 = clock.p1;
> -		crtc->new_config->dpll.p2 = clock.p2;
> +		crtc_state->dpll.n = clock.n;
> +		crtc_state->dpll.m1 = clock.m1;
> +		crtc_state->dpll.m2 = clock.m2;
> +		crtc_state->dpll.p1 = clock.p1;
> +		crtc_state->dpll.p2 = clock.p2;
>  	}
>  
>  	if (IS_GEN2(dev)) {
> -		i8xx_update_pll(crtc,
> +		i8xx_update_pll(crtc, crtc_state,
>  				has_reduced_clock ? &reduced_clock : NULL,
>  				num_connectors);
>  	} else if (IS_CHERRYVIEW(dev)) {
> -		chv_update_pll(crtc, crtc->new_config);
> +		chv_update_pll(crtc, crtc_state);
>  	} else if (IS_VALLEYVIEW(dev)) {
> -		vlv_update_pll(crtc, crtc->new_config);
> +		vlv_update_pll(crtc, crtc_state);
>  	} else {
> -		i9xx_update_pll(crtc,
> +		i9xx_update_pll(crtc, crtc_state,
>  				has_reduced_clock ? &reduced_clock : NULL,
>  				num_connectors);
>  	}
> @@ -7260,6 +7265,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
>  }
>  
>  static bool ironlake_compute_clocks(struct drm_crtc *crtc,
> +				    struct intel_crtc_state *crtc_state,
>  				    intel_clock_t *clock,
>  				    bool *has_reduced_clock,
>  				    intel_clock_t *reduced_clock)
> @@ -7282,7 +7288,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
>  	 */
>  	limit = intel_limit(intel_crtc, refclk);
>  	ret = dev_priv->display.find_dpll(limit, intel_crtc,
> -					  intel_crtc->new_config->port_clock,
> +					  crtc_state->port_clock,
>  					  refclk, NULL, clock);
>  	if (!ret)
>  		return false;
> @@ -7321,6 +7327,7 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
>  }
>  
>  static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
> +				      struct intel_crtc_state *crtc_state,
>  				      u32 *fp,
>  				      intel_clock_t *reduced_clock, u32 *fp2)
>  {
> @@ -7358,10 +7365,10 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
>  		     dev_priv->vbt.lvds_ssc_freq == 100000) ||
>  		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
>  			factor = 25;
> -	} else if (intel_crtc->new_config->sdvo_tv_clock)
> +	} else if (crtc_state->sdvo_tv_clock)
>  		factor = 20;
>  
> -	if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
> +	if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
>  		*fp |= FP_CB_TUNE;
>  
>  	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
> @@ -7374,20 +7381,20 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
>  	else
>  		dpll |= DPLLB_MODE_DAC_SERIAL;
>  
> -	dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
> +	dpll |= (crtc_state->pixel_multiplier - 1)
>  		<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
>  
>  	if (is_sdvo)
>  		dpll |= DPLL_SDVO_HIGH_SPEED;
> -	if (intel_crtc->new_config->has_dp_encoder)
> +	if (crtc_state->has_dp_encoder)
>  		dpll |= DPLL_SDVO_HIGH_SPEED;
>  
>  	/* compute bitmask from p1 value */
> -	dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
>  	/* also FPA1 */
> -	dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
> +	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
>  
> -	switch (intel_crtc->new_config->dpll.p2) {
> +	switch (crtc_state->dpll.p2) {
>  	case 5:
>  		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
>  		break;
> @@ -7410,7 +7417,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
>  	return dpll | DPLL_VCO_ENABLE;
>  }
>  
> -static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
> +static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
> +				       struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	intel_clock_t clock, reduced_clock;
> @@ -7424,39 +7432,39 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
>  	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
>  	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
>  
> -	ok = ironlake_compute_clocks(&crtc->base, &clock,
> +	ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
>  				     &has_reduced_clock, &reduced_clock);
> -	if (!ok && !crtc->new_config->clock_set) {
> +	if (!ok && !crtc_state->clock_set) {
>  		DRM_ERROR("Couldn't find PLL settings for mode!\n");
>  		return -EINVAL;
>  	}
>  	/* Compat-code for transition, will disappear. */
> -	if (!crtc->new_config->clock_set) {
> -		crtc->new_config->dpll.n = clock.n;
> -		crtc->new_config->dpll.m1 = clock.m1;
> -		crtc->new_config->dpll.m2 = clock.m2;
> -		crtc->new_config->dpll.p1 = clock.p1;
> -		crtc->new_config->dpll.p2 = clock.p2;
> +	if (!crtc_state->clock_set) {
> +		crtc_state->dpll.n = clock.n;
> +		crtc_state->dpll.m1 = clock.m1;
> +		crtc_state->dpll.m2 = clock.m2;
> +		crtc_state->dpll.p1 = clock.p1;
> +		crtc_state->dpll.p2 = clock.p2;
>  	}
>  
>  	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
> -	if (crtc->new_config->has_pch_encoder) {
> -		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
> +	if (crtc_state->has_pch_encoder) {
> +		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
>  		if (has_reduced_clock)
>  			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
>  
> -		dpll = ironlake_compute_dpll(crtc,
> +		dpll = ironlake_compute_dpll(crtc, crtc_state,
>  					     &fp, &reduced_clock,
>  					     has_reduced_clock ? &fp2 : NULL);
>  
> -		crtc->new_config->dpll_hw_state.dpll = dpll;
> -		crtc->new_config->dpll_hw_state.fp0 = fp;
> +		crtc_state->dpll_hw_state.dpll = dpll;
> +		crtc_state->dpll_hw_state.fp0 = fp;
>  		if (has_reduced_clock)
> -			crtc->new_config->dpll_hw_state.fp1 = fp2;
> +			crtc_state->dpll_hw_state.fp1 = fp2;
>  		else
> -			crtc->new_config->dpll_hw_state.fp1 = fp;
> +			crtc_state->dpll_hw_state.fp1 = fp;
>  
> -		pll = intel_get_shared_dpll(crtc);
> +		pll = intel_get_shared_dpll(crtc, crtc_state);
>  		if (pll == NULL) {
>  			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
>  					 pipe_name(crtc->pipe));
> @@ -7967,9 +7975,10 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
>  	intel_prepare_ddi(dev);
>  }
>  
> -static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
> +static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> +				      struct intel_crtc_state *crtc_state)
>  {
> -	if (!intel_ddi_pll_select(crtc))
> +	if (!intel_ddi_pll_select(crtc, crtc_state))
>  		return -EINVAL;
>  
>  	crtc->lowfreq_avail = false;
> @@ -10961,7 +10970,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
>  			goto done;
>  
>  		for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
> -			ret = dev_priv->display.crtc_compute_clock(intel_crtc);
> +			struct intel_crtc_state *state = intel_crtc->new_config;
> +			ret = dev_priv->display.crtc_compute_clock(intel_crtc,
> +								   state);
>  			if (ret) {
>  				intel_shared_dpll_abort_config(dev_priv);
>  				goto done;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c55c454..0a84667 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -818,7 +818,8 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
>  				       enum transcoder cpu_transcoder);
>  void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
>  void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
> -bool intel_ddi_pll_select(struct intel_crtc *crtc);
> +bool intel_ddi_pll_select(struct intel_crtc *crtc,
> +			  struct intel_crtc_state *crtc_state);
>  void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
>  void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
>  bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
> @@ -929,7 +930,8 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  			bool state);
>  #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
>  #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
> -struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
> +struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
> +						struct intel_crtc_state *state);
>  void intel_put_shared_dpll(struct intel_crtc *crtc);
>  
>  void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> [e-mail]
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d60d38..c1a9af9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -500,7 +500,8 @@  struct drm_i915_display_funcs {
 				struct intel_crtc_state *);
 	void (*get_plane_config)(struct intel_crtc *,
 				 struct intel_plane_config *);
-	int (*crtc_compute_clock)(struct intel_crtc *crtc);
+	int (*crtc_compute_clock)(struct intel_crtc *crtc,
+				  struct intel_crtc_state *crtc_state);
 	void (*crtc_enable)(struct drm_crtc *crtc);
 	void (*crtc_disable)(struct drm_crtc *crtc);
 	void (*off)(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 79c9776..970ca30 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -904,6 +904,7 @@  hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 
 static bool
 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
+		   struct intel_crtc_state *crtc_state,
 		   struct intel_encoder *intel_encoder,
 		   int clock)
 {
@@ -918,16 +919,16 @@  hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 		      WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 		      WRPLL_DIVIDER_POST(p);
 
-		intel_crtc->new_config->dpll_hw_state.wrpll = val;
+		crtc_state->dpll_hw_state.wrpll = val;
 
-		pll = intel_get_shared_dpll(intel_crtc);
+		pll = intel_get_shared_dpll(intel_crtc, crtc_state);
 		if (pll == NULL) {
 			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 					 pipe_name(intel_crtc->pipe));
 			return false;
 		}
 
-		intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
+		crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 	}
 
 	return true;
@@ -1090,6 +1091,7 @@  found:
 
 static bool
 skl_ddi_pll_select(struct intel_crtc *intel_crtc,
+		   struct intel_crtc_state *crtc_state,
 		   struct intel_encoder *intel_encoder,
 		   int clock)
 {
@@ -1139,11 +1141,11 @@  skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 	} else /* eDP */
 		return true;
 
-	intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1;
-	intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1;
-	intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2;
+	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
+	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
+	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
 
-	pll = intel_get_shared_dpll(intel_crtc);
+	pll = intel_get_shared_dpll(intel_crtc, crtc_state);
 	if (pll == NULL) {
 		DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 				 pipe_name(intel_crtc->pipe));
@@ -1151,7 +1153,7 @@  skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 	}
 
 	/* shared DPLL id 0 is DPLL 1 */
-	intel_crtc->new_config->ddi_pll_sel = pll->id + 1;
+	crtc_state->ddi_pll_sel = pll->id + 1;
 
 	return true;
 }
@@ -1163,17 +1165,20 @@  skl_ddi_pll_select(struct intel_crtc *intel_crtc,
  * For private DPLLs, compute_config() should do the selection for us. This
  * function should be folded into compute_config() eventually.
  */
-bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
+bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
+			  struct intel_crtc_state *crtc_state)
 {
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct intel_encoder *intel_encoder =
 		intel_ddi_get_crtc_new_encoder(intel_crtc);
-	int clock = intel_crtc->new_config->port_clock;
+	int clock = crtc_state->port_clock;
 
 	if (IS_SKYLAKE(dev))
-		return skl_ddi_pll_select(intel_crtc, intel_encoder, clock);
+		return skl_ddi_pll_select(intel_crtc, crtc_state,
+					  intel_encoder, clock);
 	else
-		return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
+		return hsw_ddi_pll_select(intel_crtc, crtc_state,
+					  intel_encoder, clock);
 }
 
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f836f67..3bceacb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3858,7 +3858,8 @@  void intel_put_shared_dpll(struct intel_crtc *crtc)
 	crtc->config.shared_dpll = DPLL_ID_PRIVATE;
 }
 
-struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
+struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
+						struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 	struct intel_shared_dpll *pll;
@@ -3884,7 +3885,7 @@  struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
 		if (pll->new_config->crtc_mask == 0)
 			continue;
 
-		if (memcmp(&crtc->new_config->dpll_hw_state,
+		if (memcmp(&crtc_state->dpll_hw_state,
 			   &pll->new_config->hw_state,
 			   sizeof(pll->new_config->hw_state)) == 0) {
 			DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
@@ -3909,9 +3910,9 @@  struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
 
 found:
 	if (pll->new_config->crtc_mask == 0)
-		pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
+		pll->new_config->hw_state = crtc_state->dpll_hw_state;
 
-	crtc->new_config->shared_dpll = i;
+	crtc_state->shared_dpll = i;
 	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
 			 pipe_name(crtc->pipe));
 
@@ -5726,30 +5727,31 @@  static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
 }
 
 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
+				     struct intel_crtc_state *crtc_state,
 				     intel_clock_t *reduced_clock)
 {
 	struct drm_device *dev = crtc->base.dev;
 	u32 fp, fp2 = 0;
 
 	if (IS_PINEVIEW(dev)) {
-		fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
+		fp = pnv_dpll_compute_fp(&crtc_state->dpll);
 		if (reduced_clock)
 			fp2 = pnv_dpll_compute_fp(reduced_clock);
 	} else {
-		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
+		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
 		if (reduced_clock)
 			fp2 = i9xx_dpll_compute_fp(reduced_clock);
 	}
 
-	crtc->new_config->dpll_hw_state.fp0 = fp;
+	crtc_state->dpll_hw_state.fp0 = fp;
 
 	crtc->lowfreq_avail = false;
 	if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
 	    reduced_clock && i915.powersave) {
-		crtc->new_config->dpll_hw_state.fp1 = fp2;
+		crtc_state->dpll_hw_state.fp1 = fp2;
 		crtc->lowfreq_avail = true;
 	} else {
-		crtc->new_config->dpll_hw_state.fp1 = fp;
+		crtc_state->dpll_hw_state.fp1 = fp;
 	}
 }
 
@@ -6084,6 +6086,7 @@  void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
 }
 
 static void i9xx_update_pll(struct intel_crtc *crtc,
+			    struct intel_crtc_state *crtc_state,
 			    intel_clock_t *reduced_clock,
 			    int num_connectors)
 {
@@ -6091,9 +6094,9 @@  static void i9xx_update_pll(struct intel_crtc *crtc,
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 dpll;
 	bool is_sdvo;
-	struct dpll *clock = &crtc->new_config->dpll;
+	struct dpll *clock = &crtc_state->dpll;
 
-	i9xx_update_pll_dividers(crtc, reduced_clock);
+	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 
 	is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
 		intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
@@ -6106,14 +6109,14 @@  static void i9xx_update_pll(struct intel_crtc *crtc,
 		dpll |= DPLLB_MODE_DAC_SERIAL;
 
 	if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
-		dpll |= (crtc->new_config->pixel_multiplier - 1)
+		dpll |= (crtc_state->pixel_multiplier - 1)
 			<< SDVO_MULTIPLIER_SHIFT_HIRES;
 	}
 
 	if (is_sdvo)
 		dpll |= DPLL_SDVO_HIGH_SPEED;
 
-	if (crtc->new_config->has_dp_encoder)
+	if (crtc_state->has_dp_encoder)
 		dpll |= DPLL_SDVO_HIGH_SPEED;
 
 	/* compute bitmask from p1 value */
@@ -6141,7 +6144,7 @@  static void i9xx_update_pll(struct intel_crtc *crtc,
 	if (INTEL_INFO(dev)->gen >= 4)
 		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
 
-	if (crtc->new_config->sdvo_tv_clock)
+	if (crtc_state->sdvo_tv_clock)
 		dpll |= PLL_REF_INPUT_TVCLKINBC;
 	else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
 		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
@@ -6150,25 +6153,26 @@  static void i9xx_update_pll(struct intel_crtc *crtc,
 		dpll |= PLL_REF_INPUT_DREFCLK;
 
 	dpll |= DPLL_VCO_ENABLE;
-	crtc->new_config->dpll_hw_state.dpll = dpll;
+	crtc_state->dpll_hw_state.dpll = dpll;
 
 	if (INTEL_INFO(dev)->gen >= 4) {
-		u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
+		u32 dpll_md = (crtc_state->pixel_multiplier - 1)
 			<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
-		crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
+		crtc_state->dpll_hw_state.dpll_md = dpll_md;
 	}
 }
 
 static void i8xx_update_pll(struct intel_crtc *crtc,
+			    struct intel_crtc_state *crtc_state,
 			    intel_clock_t *reduced_clock,
 			    int num_connectors)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 dpll;
-	struct dpll *clock = &crtc->new_config->dpll;
+	struct dpll *clock = &crtc_state->dpll;
 
-	i9xx_update_pll_dividers(crtc, reduced_clock);
+	i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
 
 	dpll = DPLL_VGA_MODE_DIS;
 
@@ -6193,7 +6197,7 @@  static void i8xx_update_pll(struct intel_crtc *crtc,
 		dpll |= PLL_REF_INPUT_DREFCLK;
 
 	dpll |= DPLL_VCO_ENABLE;
-	crtc->new_config->dpll_hw_state.dpll = dpll;
+	crtc_state->dpll_hw_state.dpll = dpll;
 }
 
 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
@@ -6389,7 +6393,8 @@  static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 	POSTING_READ(PIPECONF(intel_crtc->pipe));
 }
 
-static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
+static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
+				   struct intel_crtc_state *crtc_state)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6421,7 +6426,7 @@  static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
 	if (is_dsi)
 		return 0;
 
-	if (!crtc->new_config->clock_set) {
+	if (!crtc_state->clock_set) {
 		refclk = i9xx_get_refclk(crtc, num_connectors);
 
 		/*
@@ -6432,7 +6437,7 @@  static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
 		 */
 		limit = intel_limit(crtc, refclk);
 		ok = dev_priv->display.find_dpll(limit, crtc,
-						 crtc->new_config->port_clock,
+						 crtc_state->port_clock,
 						 refclk, NULL, &clock);
 		if (!ok) {
 			DRM_ERROR("Couldn't find PLL settings for mode!\n");
@@ -6453,23 +6458,23 @@  static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
 							    &reduced_clock);
 		}
 		/* Compat-code for transition, will disappear. */
-		crtc->new_config->dpll.n = clock.n;
-		crtc->new_config->dpll.m1 = clock.m1;
-		crtc->new_config->dpll.m2 = clock.m2;
-		crtc->new_config->dpll.p1 = clock.p1;
-		crtc->new_config->dpll.p2 = clock.p2;
+		crtc_state->dpll.n = clock.n;
+		crtc_state->dpll.m1 = clock.m1;
+		crtc_state->dpll.m2 = clock.m2;
+		crtc_state->dpll.p1 = clock.p1;
+		crtc_state->dpll.p2 = clock.p2;
 	}
 
 	if (IS_GEN2(dev)) {
-		i8xx_update_pll(crtc,
+		i8xx_update_pll(crtc, crtc_state,
 				has_reduced_clock ? &reduced_clock : NULL,
 				num_connectors);
 	} else if (IS_CHERRYVIEW(dev)) {
-		chv_update_pll(crtc, crtc->new_config);
+		chv_update_pll(crtc, crtc_state);
 	} else if (IS_VALLEYVIEW(dev)) {
-		vlv_update_pll(crtc, crtc->new_config);
+		vlv_update_pll(crtc, crtc_state);
 	} else {
-		i9xx_update_pll(crtc,
+		i9xx_update_pll(crtc, crtc_state,
 				has_reduced_clock ? &reduced_clock : NULL,
 				num_connectors);
 	}
@@ -7260,6 +7265,7 @@  static void haswell_set_pipeconf(struct drm_crtc *crtc)
 }
 
 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
+				    struct intel_crtc_state *crtc_state,
 				    intel_clock_t *clock,
 				    bool *has_reduced_clock,
 				    intel_clock_t *reduced_clock)
@@ -7282,7 +7288,7 @@  static bool ironlake_compute_clocks(struct drm_crtc *crtc,
 	 */
 	limit = intel_limit(intel_crtc, refclk);
 	ret = dev_priv->display.find_dpll(limit, intel_crtc,
-					  intel_crtc->new_config->port_clock,
+					  crtc_state->port_clock,
 					  refclk, NULL, clock);
 	if (!ret)
 		return false;
@@ -7321,6 +7327,7 @@  static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
 }
 
 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
+				      struct intel_crtc_state *crtc_state,
 				      u32 *fp,
 				      intel_clock_t *reduced_clock, u32 *fp2)
 {
@@ -7358,10 +7365,10 @@  static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 		     dev_priv->vbt.lvds_ssc_freq == 100000) ||
 		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
 			factor = 25;
-	} else if (intel_crtc->new_config->sdvo_tv_clock)
+	} else if (crtc_state->sdvo_tv_clock)
 		factor = 20;
 
-	if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
+	if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
 		*fp |= FP_CB_TUNE;
 
 	if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
@@ -7374,20 +7381,20 @@  static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	else
 		dpll |= DPLLB_MODE_DAC_SERIAL;
 
-	dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
+	dpll |= (crtc_state->pixel_multiplier - 1)
 		<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
 
 	if (is_sdvo)
 		dpll |= DPLL_SDVO_HIGH_SPEED;
-	if (intel_crtc->new_config->has_dp_encoder)
+	if (crtc_state->has_dp_encoder)
 		dpll |= DPLL_SDVO_HIGH_SPEED;
 
 	/* compute bitmask from p1 value */
-	dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
 	/* also FPA1 */
-	dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+	dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
 
-	switch (intel_crtc->new_config->dpll.p2) {
+	switch (crtc_state->dpll.p2) {
 	case 5:
 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 		break;
@@ -7410,7 +7417,8 @@  static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	return dpll | DPLL_VCO_ENABLE;
 }
 
-static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
+static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
+				       struct intel_crtc_state *crtc_state)
 {
 	struct drm_device *dev = crtc->base.dev;
 	intel_clock_t clock, reduced_clock;
@@ -7424,39 +7432,39 @@  static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
 	WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
 	     "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
 
-	ok = ironlake_compute_clocks(&crtc->base, &clock,
+	ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
 				     &has_reduced_clock, &reduced_clock);
-	if (!ok && !crtc->new_config->clock_set) {
+	if (!ok && !crtc_state->clock_set) {
 		DRM_ERROR("Couldn't find PLL settings for mode!\n");
 		return -EINVAL;
 	}
 	/* Compat-code for transition, will disappear. */
-	if (!crtc->new_config->clock_set) {
-		crtc->new_config->dpll.n = clock.n;
-		crtc->new_config->dpll.m1 = clock.m1;
-		crtc->new_config->dpll.m2 = clock.m2;
-		crtc->new_config->dpll.p1 = clock.p1;
-		crtc->new_config->dpll.p2 = clock.p2;
+	if (!crtc_state->clock_set) {
+		crtc_state->dpll.n = clock.n;
+		crtc_state->dpll.m1 = clock.m1;
+		crtc_state->dpll.m2 = clock.m2;
+		crtc_state->dpll.p1 = clock.p1;
+		crtc_state->dpll.p2 = clock.p2;
 	}
 
 	/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
-	if (crtc->new_config->has_pch_encoder) {
-		fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
+	if (crtc_state->has_pch_encoder) {
+		fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
 		if (has_reduced_clock)
 			fp2 = i9xx_dpll_compute_fp(&reduced_clock);
 
-		dpll = ironlake_compute_dpll(crtc,
+		dpll = ironlake_compute_dpll(crtc, crtc_state,
 					     &fp, &reduced_clock,
 					     has_reduced_clock ? &fp2 : NULL);
 
-		crtc->new_config->dpll_hw_state.dpll = dpll;
-		crtc->new_config->dpll_hw_state.fp0 = fp;
+		crtc_state->dpll_hw_state.dpll = dpll;
+		crtc_state->dpll_hw_state.fp0 = fp;
 		if (has_reduced_clock)
-			crtc->new_config->dpll_hw_state.fp1 = fp2;
+			crtc_state->dpll_hw_state.fp1 = fp2;
 		else
-			crtc->new_config->dpll_hw_state.fp1 = fp;
+			crtc_state->dpll_hw_state.fp1 = fp;
 
-		pll = intel_get_shared_dpll(crtc);
+		pll = intel_get_shared_dpll(crtc, crtc_state);
 		if (pll == NULL) {
 			DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 					 pipe_name(crtc->pipe));
@@ -7967,9 +7975,10 @@  void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 	intel_prepare_ddi(dev);
 }
 
-static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
+static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
+				      struct intel_crtc_state *crtc_state)
 {
-	if (!intel_ddi_pll_select(crtc))
+	if (!intel_ddi_pll_select(crtc, crtc_state))
 		return -EINVAL;
 
 	crtc->lowfreq_avail = false;
@@ -10961,7 +10970,9 @@  static int __intel_set_mode(struct drm_crtc *crtc,
 			goto done;
 
 		for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
-			ret = dev_priv->display.crtc_compute_clock(intel_crtc);
+			struct intel_crtc_state *state = intel_crtc->new_config;
+			ret = dev_priv->display.crtc_compute_clock(intel_crtc,
+								   state);
 			if (ret) {
 				intel_shared_dpll_abort_config(dev_priv);
 				goto done;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c55c454..0a84667 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -818,7 +818,8 @@  void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 				       enum transcoder cpu_transcoder);
 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
-bool intel_ddi_pll_select(struct intel_crtc *crtc);
+bool intel_ddi_pll_select(struct intel_crtc *crtc,
+			  struct intel_crtc_state *crtc_state);
 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
@@ -929,7 +930,8 @@  void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			bool state);
 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
-struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc);
+struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
+						struct intel_crtc_state *state);
 void intel_put_shared_dpll(struct intel_crtc *crtc);
 
 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,