From patchwork Mon Dec 8 15:21:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 5456991 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3D5AD9F30B for ; Mon, 8 Dec 2014 15:21:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6DD012013D for ; Mon, 8 Dec 2014 15:21:33 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 994042017D for ; Mon, 8 Dec 2014 15:21:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B7376E705; Mon, 8 Dec 2014 07:21:32 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id BAECC6E703 for ; Mon, 8 Dec 2014 07:21:30 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 08 Dec 2014 07:21:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,539,1413270000"; d="scan'208";a="634467737" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by fmsmga001.fm.intel.com with ESMTP; 08 Dec 2014 07:21:27 -0800 Received: from localhost (ander-mobl1.fi.intel.com [10.237.72.54]) by linux.intel.com (Postfix) with ESMTP id 3968B6A408D; Mon, 8 Dec 2014 07:20:28 -0800 (PST) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Mon, 8 Dec 2014 17:21:06 +0200 Message-Id: <1418052069-14831-6-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1418052069-14831-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1418052069-14831-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira , shuang.he@linux.intel.com Subject: [Intel-gfx] [RFC][PATCH 5/8] drm/i915: Don't access to crtc->new_config from intel_mode_max_pixclk() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP So that we can get rid of the new_config pointer later. --- drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index da5af23..a9f3034 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4897,27 +4897,39 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, } /* compute the max pixel clock for new configuration */ -static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv, + struct intel_crtc *mode_set_crtc, + struct intel_crtc_state *crtc_new_state) { struct drm_device *dev = dev_priv->dev; struct intel_crtc *intel_crtc; int max_pixclk = 0; + int pixclk; for_each_intel_crtc(dev, intel_crtc) { - if (intel_crtc->new_enabled) - max_pixclk = max(max_pixclk, - intel_crtc->new_config->base.adjusted_mode.crtc_clock); + if (!intel_crtc->new_enabled) + continue; + + if (intel_crtc == mode_set_crtc) + pixclk = crtc_new_state->base.adjusted_mode.crtc_clock; + else + pixclk = intel_crtc->config->base.adjusted_mode.crtc_clock; + + max_pixclk = max(max_pixclk, pixclk); } return max_pixclk; } static void valleyview_modeset_global_pipes(struct drm_device *dev, - unsigned *prepare_pipes) + unsigned *prepare_pipes, + struct intel_crtc *mode_set_crtc, + struct intel_crtc_state *crtc_new_state) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc; - int max_pixclk = intel_mode_max_pixclk(dev_priv); + int max_pixclk = + intel_mode_max_pixclk(dev_priv, mode_set_crtc, crtc_new_state); if (valleyview_calc_cdclk(dev_priv, max_pixclk) == dev_priv->vlv_cdclk_freq) @@ -4932,7 +4944,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev, static void valleyview_modeset_global_resources(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int max_pixclk = intel_mode_max_pixclk(dev_priv); + int max_pixclk = intel_mode_max_pixclk(dev_priv, NULL, NULL); int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); if (req_cdclk != dev_priv->vlv_cdclk_freq) { @@ -10956,7 +10968,9 @@ static int __intel_set_mode(struct drm_crtc *crtc, * adjusted_mode bits in the crtc directly. */ if (IS_VALLEYVIEW(dev)) { - valleyview_modeset_global_pipes(dev, &prepare_pipes); + valleyview_modeset_global_pipes(dev, &prepare_pipes, + to_intel_crtc(crtc), + pipe_config); /* may have added more to prepare_pipes than we should */ prepare_pipes &= ~disable_pipes;