From patchwork Mon Dec 8 16:09:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 5457291 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5CD459F1C5 for ; Mon, 8 Dec 2014 16:10:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 42DB8201B4 for ; Mon, 8 Dec 2014 16:10:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0F79720155 for ; Mon, 8 Dec 2014 16:10:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F39C06E7A8; Mon, 8 Dec 2014 08:10:30 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qg0-f53.google.com (mail-qg0-f53.google.com [209.85.192.53]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D5926E7A8 for ; Mon, 8 Dec 2014 08:10:29 -0800 (PST) Received: by mail-qg0-f53.google.com with SMTP id l89so767285qgf.26 for ; Mon, 08 Dec 2014 08:10:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f/te7GfneTZFKSJ0fWrwmUAUEffmFYzT6tHEC9KRJmA=; b=bLGKGidQhCAzTy0F3PvA3aAXvFhCr7lnnFbfEAl98LdXAEl3HMYKpTFWUPxAvCxiQ+ 1vNEbAsbLljjcV7ME8Q5RmZHsJxc3G80tKkka0vkIhi5HckO+v/EFP312cFRrwS7vfyy qMGTTZWj7POtDdZImHGCorv4JIjVKVncHkQFbNMDAMhzW3VH30UtYJefvSHgAChApTQY 4eU0jfrcd1x9OKneXzD/VNzPOOFFS74+S2S53VacxKLi9F+3hNV1JtbfGpGtIAv+MMLn npO9J6Wl+0VN2DA5zBfia6xpCy9BBTw/7NzzUaHDeXC3tDRYVc5RyhWBIk/gXpHlaOb1 lRfw== X-Received: by 10.140.44.97 with SMTP id f88mr51256023qga.88.1418055029223; Mon, 08 Dec 2014 08:10:29 -0800 (PST) Received: from localhost.localdomain ([187.95.104.42]) by mx.google.com with ESMTPSA id d9sm38189123qam.26.2014.12.08.08.10.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Dec 2014 08:10:28 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Mon, 8 Dec 2014 14:09:11 -0200 Message-Id: <1418054960-1403-3-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1418054960-1403-1-git-send-email-przanoni@gmail.com> References: <1418054960-1403-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni , Rodrigo Vivi Subject: [Intel-gfx] [PATCH 02/11] drm/i915: Introduce FBC DocBook. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rodrigo Vivi No functional changes. v2 (Paulo): Rebase. Signed-off-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- Documentation/DocBook/drm.tmpl | 5 ++++ drivers/gpu/drm/i915/intel_fbc.c | 57 ++++++++++++++++++++++++++++++++++------ 2 files changed, 54 insertions(+), 8 deletions(-) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 85287cb..8b780ab 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -3926,6 +3926,11 @@ int num_ioctls; !Idrivers/gpu/drm/i915/intel_psr.c + Frame Buffer Compression (FBC) +!Pdrivers/gpu/drm/i915/intel_fbc.c Frame Buffer Compression (FBC) +!Idrivers/gpu/drm/i915/intel_fbc.c + + DPIO !Pdrivers/gpu/drm/i915/i915_reg.h DPIO diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index f1eeb86..7686573 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -21,20 +21,31 @@ * DEALINGS IN THE SOFTWARE. */ -#include "intel_drv.h" -#include "i915_drv.h" - -/* FBC, or Frame Buffer Compression, is a technique employed to compress the - * framebuffer contents in-memory, aiming at reducing the required bandwidth +/** + * DOC: Frame Buffer Compression (FBC) + * + * FBC is a technique employed to compress the framebuffer contents + * in-memory, aiming at reducing the required bandwidth * during in-memory transfers and, therefore, reduce the power packet. * + * FBC is primarily a memory power savings technology. That is the major + * benefit is to the memory power while displaying the processor graphics + * information to the display. FBC works by compressing the amount of memory + * used by the display. It means that it is total transparent to user space. + * * The benefits of FBC are mostly visible with solid backgrounds and - * variation-less patterns. + * variation-less patterns. It comes from keeping the memory footprint small + * and having fewer memory pages opened and accessed for refreshing the display. * - * FBC-related functionality can be enabled by the means of the - * i915.i915_fbc_enable parameter + * i915 is responsible to reserve stolen memory for FBC and configure its + * offset on proper register. The hardware takes care of all + * compress/decompress. However there are many known cases where we have to + * forcibly disable it to allow proper screen updates. */ +#include "intel_drv.h" +#include "i915_drv.h" + static void i8xx_fbc_disable(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -318,6 +329,12 @@ static void gen7_fbc_enable(struct drm_crtc *crtc) DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); } +/** + * intel_fbc_enabled - Is FBC enabled? + * @dev: the drm_device + * + * This function is used to verify the current state of FBC. + */ bool intel_fbc_enabled(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -325,6 +342,18 @@ bool intel_fbc_enabled(struct drm_device *dev) return dev_priv->fbc.enabled; } +/** + * bdw_fbc_sw_flush - FBC Software Flush for Broadwell. + * @dev: the drm_device + * @value: Value to be set on MSG_FBC_REND_STATE. Possible values are + * FBC_REND_NUKE and FBC_REND_CACHE_CLEAN. + * + * This function is needed on Broadwell to perform Nuke or Cache clean on + * software side over MMIO. + * On Broadwell, due a hardware bug, MSG_FBC_REND_STATE stay in a forbidden + * address that has a huge risk of causing GPU Hangs if set with LRI on some + * command streamers. + */ void bdw_fbc_sw_flush(struct drm_device *dev, u32 value) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -429,6 +458,12 @@ static void intel_fbc_enable(struct drm_crtc *crtc) schedule_delayed_work(&work->work, msecs_to_jiffies(50)); } +/** + * intel_fbc_disable - disable FBC + * @dev: the drm_device + * + * This function disables FBC. + */ void intel_fbc_disable(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -643,6 +678,12 @@ out_disable: i915_gem_stolen_cleanup_compression(dev); } +/** + * intel_fbc_init - Initialize FBC + * @dev_priv: the i915 device + * + * This function might be called during PM init process. + */ void intel_fbc_init(struct drm_i915_private *dev_priv) { if (!HAS_FBC(dev_priv)) {