| Message ID | 1418394418-10517-3-git-send-email-damien.lespiau@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 364/364 364/364
ILK +3-2 362/366 363/366
SNB 448/450 448/450
IVB 497/498 497/498
BYT -2 289/289 287/289
HSW -1 563/564 562/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
ILK igt_kms_flip_nonexisting-fb DMESG_WARN(1, M26)PASS(4, M37M26) PASS(1, M26)
ILK igt_kms_flip_rcs-flip-vs-panning-interruptible DMESG_WARN(2, M26)PASS(3, M37M26) PASS(1, M26)
ILK igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible DMESG_WARN(1, M26)PASS(3, M26M37) PASS(1, M26)
*ILK igt_kms_flip_plain-flip-ts-check-interruptible PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_wf_vblank-ts-check PASS(2, M26) DMESG_WARN(1, M26)
*BYT igt_drm_import_export_flink PASS(2, M48M50) DMESG_WARN(1, M50)
*BYT igt_drm_vma_limiter_gtt PASS(2, M48M50) TIMEOUT(1, M50)
*HSW igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked PASS(2, M40M19) DMESG_WARN(1, M19)
Note: You need to pay more attention to line start with '*'
On 13 December 2014 at 00:26, Damien Lespiau <damien.lespiau@intel.com> wrote: > I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to > HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good > chance to be working as well as prevous platforms. > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Seems like it should work to me, right until you release a gen 9 that doesn't do MST, but hopefully that won't happen, since 4k might matter even for the atom chipsets. Reviewed-by: Dave Airlie <airlied@redhat.com> > - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { > if (port == PORT_B || port == PORT_C || port == PORT_D) { > intel_dp_mst_encoder_init(intel_dig_port, > intel_connector->base.base.id); > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Dec 12, 2014 at 02:26:58PM +0000, Damien Lespiau wrote: > I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to > HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good > chance to be working as well as prevous platforms. > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 3fc3296..8e276c4 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -5085,7 +5085,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > intel_dp_aux_init(intel_dp, intel_connector); > > /* init MST on ports that can support it */ > - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { > + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { HAS_DDI might be a nice bikeshed here if you're bored. Applied both to dinq. Thanks, Daniel > if (port == PORT_B || port == PORT_C || port == PORT_D) { > intel_dp_mst_encoder_init(intel_dig_port, > intel_connector->base.base.id); > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3fc3296..8e276c4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5085,7 +5085,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp_aux_init(intel_dp, intel_connector); /* init MST on ports that can support it */ - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { if (port == PORT_B || port == PORT_C || port == PORT_D) { intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good chance to be working as well as prevous platforms. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)