| Message ID | 1418921141-18035-1-git-send-email-david.s.gordon@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -1 364/364 363/364
ILK -7 364/366 357/366
SNB -1 448/450 447/450
IVB -1 497/498 496/498
BYT -1 289/289 288/289
HSW -1 563/564 562/564
BDW -1 416/417 415/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_exec_blt NRUN(5, M23M7M25)PASS(1, M25) NRUN(1, M23)
ILK igt_gem_exec_blt NRUN(7, M37M26)PASS(1, M26) NRUN(1, M26)
ILK igt_kms_render_direct-render DMESG_WARN(1, M26)PASS(3, M26) DMESG_WARN(1, M26)
ILK igt_kms_flip_blocking-absolute-wf_vblank-interruptible DMESG_WARN(1, M26)PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_plain-flip-fb-recreate-interruptible PASS(3, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_rcs-flip-vs-dpms NSPT(1, M26)PASS(3, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_vblank-vs-hang PASS(3, M26) NSPT(1, M26)
*ILK igt_kms_flip_wf_vblank-ts-check PASS(4, M26) DMESG_WARN(1, M26)
SNB igt_gem_exec_blt NRUN(7, M35M22)PASS(1, M35) NRUN(1, M35)
IVB igt_gem_exec_blt NRUN(7, M34M21M4)PASS(1, M34) NRUN(1, M21)
BYT igt_gem_exec_blt NRUN(7, M48M49M50M51)PASS(1, M48) NRUN(1, M49)
HSW igt_gem_exec_blt NRUN(7, M40M20M19)PASS(1, M40) NRUN(1, M19)
BDW igt_gem_exec_blt NRUN(6, M30M28)PASS(1, M28) NRUN(1, M28)
Note: You need to pay more attention to line start with '*'
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index e9561de..d29b4d4 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -147,6 +147,13 @@ static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, gen6_gt_check_fifodbg(dev_priv); } +static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv) +{ + u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL); + + return count & GT_FIFO_FREE_ENTRIES_MASK; +} + static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) { int ret = 0; @@ -154,16 +161,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) /* On VLV, FIFO will be shared by both SW and HW. * So, we need to read the FREE_ENTRIES everytime */ if (IS_VALLEYVIEW(dev_priv->dev)) - dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; - u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + u32 fifo = fifo_free_entries(dev_priv); + while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { udelay(10); - fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; + fifo = fifo_free_entries(dev_priv); } if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) ++ret; @@ -505,8 +511,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) if (IS_GEN6(dev) || IS_GEN7(dev)) dev_priv->uncore.fifo_count = - __raw_i915_read32(dev_priv, GTFIFOCTL) & - GT_FIFO_FREE_ENTRIES_MASK; + fifo_free_entries(dev_priv); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
When querying the GTFIFOCTL register to check the FIFO space, the read value must be masked. The operation is repeated explicitly in several places. This change refactors the read-and-mask code into a function call. v2: rebase to latest drm-intel-nightly Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_uncore.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-)