From patchwork Tue Dec 23 12:35:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 5533081 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 266A4BEEA8 for ; Tue, 23 Dec 2014 12:36:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5446F2018E for ; Tue, 23 Dec 2014 12:36:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 809D120165 for ; Tue, 23 Dec 2014 12:36:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1061B6E445; Tue, 23 Dec 2014 04:36:41 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-vc0-f178.google.com (mail-vc0-f178.google.com [209.85.220.178]) by gabe.freedesktop.org (Postfix) with ESMTP id 9CCB96E445 for ; Tue, 23 Dec 2014 04:36:39 -0800 (PST) Received: by mail-vc0-f178.google.com with SMTP id hq11so2313356vcb.9 for ; Tue, 23 Dec 2014 04:36:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rxuXBmjmRE7hf7PWdNCVi4paQKEnBGpTlnliHBUmXCg=; b=YAQu5FKlkp+/30H6HFJN5kqzu7lfk2AveFjaWRzsR5A8JLfeUARAb7fIpagaCyw6K7 ijd5495iE+9LzdEXzuFJnIHMfsaffnjR1kFOT+UZAhwSDdremldKQNPABnBDEg8UwXXa LB9NHVTXiS9S2nXCgHjPivhJdE/nztgiTuneYkQoI3KAfykx6GECPjWYMgPbN3Ga3OST adqJFMA5PxDvJ9MW+8CB+/tdbm/QhYSzcttmhIplJ3t2FHGXfGOCTxg0v9RG59FrarMe 6A8xA485qYO26Af+BBdPJKuv4iSEVOze3ytG0eTZF0mE0Oc1/opkFLBlg9o3iXEvZWBQ J49A== X-Received: by 10.52.8.101 with SMTP id q5mr5468817vda.79.1419338199100; Tue, 23 Dec 2014 04:36:39 -0800 (PST) Received: from localhost.localdomain ([177.92.19.202]) by mx.google.com with ESMTPSA id at12sm4915045vdc.15.2014.12.23.04.36.37 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Dec 2014 04:36:38 -0800 (PST) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 23 Dec 2014 10:35:39 -0200 Message-Id: <1419338145-1912-4-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1419338145-1912-1-git-send-email-przanoni@gmail.com> References: <1419338145-1912-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 3/9] drm/i915: don't increment the FBC threshold at fbc_enable X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni We first set the threshold value when we're allocating the CFB, and then later at {ilk,gen7}_fbc_enable() we increment it in case we're using 16bpp. While that is correct, it is dangerous: if we rework the code a little bit in a way that allows us to call intel_fbc_enable() without necessarily calling i915_gem_stolen_setup_compression() first, we might end up incrementing threshold more than once. To prevent that, increment a temporary variable instead. We're going to need this patch for a later rework. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 5270dc4..1b10b06 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -187,14 +187,15 @@ static void ilk_fbc_enable(struct drm_crtc *crtc) struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); u32 dpfc_ctl; + int threshold = dev_priv->fbc.threshold; dev_priv->fbc.enabled = true; dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) - dev_priv->fbc.threshold++; + threshold++; - switch (dev_priv->fbc.threshold) { + switch (threshold) { case 4: case 3: dpfc_ctl |= DPFC_CTL_LIMIT_4X; @@ -258,14 +259,15 @@ static void gen7_fbc_enable(struct drm_crtc *crtc) struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); u32 dpfc_ctl; + int threshold = dev_priv->fbc.threshold; dev_priv->fbc.enabled = true; dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) - dev_priv->fbc.threshold++; + threshold++; - switch (dev_priv->fbc.threshold) { + switch (threshold) { case 4: case 3: dpfc_ctl |= DPFC_CTL_LIMIT_4X;