From patchwork Tue Jan 13 07:59:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 5618281 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A6F6FC058D for ; Tue, 13 Jan 2015 08:00:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6723720576 for ; Tue, 13 Jan 2015 08:00:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 535E420573 for ; Tue, 13 Jan 2015 08:00:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C9EC8973E; Tue, 13 Jan 2015 00:00:09 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 56E1C8973E for ; Tue, 13 Jan 2015 00:00:08 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 12 Jan 2015 23:56:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,691,1406617200"; d="scan'208";a="511413059" Received: from linux.jf.intel.com (HELO linux.intel.com) ([10.23.219.25]) by orsmga003.jf.intel.com with ESMTP; 12 Jan 2015 23:53:41 -0800 Received: from localhost (ander-mobl1.fi.intel.com [10.237.72.65]) by linux.intel.com (Postfix) with ESMTP id 5664F2C8002; Mon, 12 Jan 2015 23:59:43 -0800 (PST) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Jan 2015 09:59:43 +0200 Message-Id: <1421135983-1581-1-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 1.9.1 Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH] drm/i915: Fix all pipe->plane mappings before sanitizing crtc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If QUIRK_PIPEA_FORCE is necessary, intel_sanitize_crtc() might trigger a mode set. In that case, if pipe A is disabled and pipe B is mapped to plane B, that mode set happens before the mapping is fixed. Due to the wrong state, the call to disable pipe B disables plane A (which is already disabled) and later an assertion for plane B being enabled (while it should have been disabled) is triggered. References: https://bugs.freedesktop.org/show_bug.cgi?id=72782 Signed-off-by: Ander Conselvan de Oliveira Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/intel_display.c | 50 +++++++++++++++++++++++------------- 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d01db1b..cf87528 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13127,30 +13127,22 @@ intel_check_plane_mapping(struct intel_crtc *crtc) return true; } -static void intel_sanitize_crtc(struct intel_crtc *crtc) +static void intel_fix_plane_mapping(struct drm_device *dev) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - u32 reg; - - /* Clear any frame start delays used for debugging left by the BIOS */ - reg = PIPECONF(crtc->config.cpu_transcoder); - I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); + struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_crtc *crtc; - /* restore vblank interrupts to correct state */ - if (crtc->active) { - update_scanline_offset(crtc); - drm_vblank_on(dev, crtc->pipe); - } else - drm_vblank_off(dev, crtc->pipe); + /* gen4+ has a fixed plane -> pipe mapping.*/ + if (INTEL_INFO(dev)->gen >= 4) + return; - /* We need to sanitize the plane -> pipe mapping first because this will - * disable the crtc (and hence change the state) if it is wrong. Note - * that gen4+ has a fixed plane -> pipe mapping. */ - if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { + for_each_intel_crtc(dev, crtc) { struct intel_connector *connector; bool plane; + if (intel_check_plane_mapping(crtc)) + continue; + DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", crtc->base.base.id); @@ -13184,6 +13176,24 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) WARN_ON(crtc->active); crtc->base.enabled = false; } +} + +static void intel_sanitize_crtc(struct intel_crtc *crtc) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 reg; + + /* Clear any frame start delays used for debugging left by the BIOS */ + reg = PIPECONF(crtc->config.cpu_transcoder); + I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); + + /* restore vblank interrupts to correct state */ + if (crtc->active) { + update_scanline_offset(crtc); + drm_vblank_on(dev, crtc->pipe); + } else + drm_vblank_off(dev, crtc->pipe); if (dev_priv->quirks & QUIRK_PIPEA_FORCE && crtc->pipe == PIPE_A && !crtc->active) { @@ -13442,6 +13452,10 @@ void intel_modeset_setup_hw_state(struct drm_device *dev, intel_sanitize_encoder(encoder); } + /* We need to sanitize the plane -> pipe mapping first because this will + * disable the crtc (and hence change the state) if it is wrong. */ + intel_fix_plane_mapping(dev); + for_each_pipe(dev_priv, pipe) { crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); intel_sanitize_crtc(crtc);