| Message ID | 1421326527-24906-8-git-send-email-ander.conselvan.de.oliveira@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5586
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -1 353/353 352/353
ILK 353/353 353/353
SNB 400/422 400/422
IVB 487/487 487/487
BYT 296/296 296/296
HSW +22-2 486/508 506/508
BDW -1 402/402 401/402
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gen3_render_linear_blits PASS(4, M25M23) CRASH(1, M23)
HSW igt_kms_cursor_crc_cursor-size-change NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_kms_fence_pin_leak NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_kms_flip_dpms-vs-vblank-race DMESG_WARN(1, M40)PASS(1, M40) DMESG_WARN(1, M40)
*HSW igt_kms_flip_event_leak NSPT(2, M40)PASS(3, M20) PASS(1, M40)
HSW igt_kms_flip_flip-vs-dpms-off-vs-modeset DMESG_WARN(2, M20M40)PASS(1, M40) DMESG_WARN(1, M40)
HSW igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_lpsp_non-edp NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_cursor NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_cursor-dpms NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_dpms-non-lpsp NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_drm-resources-equal NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_fences NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_fences-dpms NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_gem-execbuf NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_gem-mmap-cpu NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_gem-mmap-gtt NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_gem-pread NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_i2c NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_modeset-non-lpsp NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_pci-d3-state NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
HSW igt_pm_rpm_rte NSPT(1, M40)PASS(4, M20M40) PASS(1, M40)
*BDW igt_gem_concurrent_blit_gtt-rcs-early-read-interruptible PASS(7, M30M28) DMESG_WARN(1, M28)
Note: You need to pay more attention to line start with '*'
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 002e5a9..b6c4667 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8931,6 +8931,7 @@ static void intel_crtc_set_state(struct intel_crtc *crtc, { kfree(crtc->config); crtc->config = crtc_state; + crtc->base.state = &crtc_state->base; } static void intel_crtc_destroy(struct drm_crtc *crtc)
So that atomic operations will reference the right crtc state. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 1 + 1 file changed, 1 insertion(+)