From patchwork Thu Jan 22 16:45:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 5686741 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E286DC058D for ; Thu, 22 Jan 2015 16:50:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0D9422021A for ; Thu, 22 Jan 2015 16:50:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 150E620219 for ; Thu, 22 Jan 2015 16:50:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 859FD6E312; Thu, 22 Jan 2015 08:50:48 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id D5B836E312 for ; Thu, 22 Jan 2015 08:50:47 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 22 Jan 2015 08:50:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,450,1418112000"; d="scan'208";a="665967159" Received: from ramaling-desktop.iind.intel.com ([10.223.26.95]) by fmsmga002.fm.intel.com with ESMTP; 22 Jan 2015 08:49:43 -0800 From: Ramalingam C To: intel-gfx@lists.freedesktop.org, rodrigo.vivi@intel.com, chris@chris-wilson.co.uk Date: Thu, 22 Jan 2015 22:15:21 +0530 Message-Id: <1421945121-11050-1-git-send-email-ramalingam.c@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <54BF9B0C.8000803@intel.com> References: <54BF9B0C.8000803@intel.com> Cc: paulo.r.zanoni@intel.com Subject: [Intel-gfx] [PATCH] drm/i915: Add debugfs entry for DRRS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vandana Kannan Adding a debugfs entry to determine if DRRS is supported or not V2: [By Ram]: Following details about the active crtc will be filled in seq-file of the debugfs 1. Encoder output type 2. DRRS Support on this CRTC 3. DRRS current state 4. Current Vrefresh Format is as follows: CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_HIGH_RR, Vrefresh: 60 CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless CRTC 1: Output: eDP, DRRS Supported: Yes (Seamless), DRRS_State: DRRS_LOW_RR, Vrefresh: 40 CRTC 2: Output: HDMI, DRRS Supported : No, VBT DRRS_type: Seamless Signed-off-by: Vandana Kannan Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/i915_debugfs.c | 93 +++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2ad4c48..47f1f65 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2819,6 +2819,98 @@ static int i915_ddb_info(struct seq_file *m, void *unused) return 0; } +static int i915_drrs_status(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = m->private; + struct drm_device *dev = node->minor->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct i915_drrs *drrs = &dev_priv->drrs; + struct intel_crtc *intel_crtc; + struct intel_encoder *intel_encoder; + int active_crtc_cnt = 0, vrefresh = 0; + + for_each_intel_crtc(dev, intel_crtc) { + if (intel_crtc->active) { + active_crtc_cnt++; + seq_puts(m, "CRTC"); + seq_put_decimal_ull(m, ' ', active_crtc_cnt); + seq_puts(m, ": "); + for_each_encoder_on_crtc(dev, &intel_crtc->base, + intel_encoder) { + /* Encoder connected on this CRTC */ + switch (intel_encoder->type) { + case INTEL_OUTPUT_EDP: + seq_puts(m, "Output: eDP, "); + break; + case INTEL_OUTPUT_DSI: + seq_puts(m, "Output: DSI, "); + break; + case INTEL_OUTPUT_HDMI: + seq_puts(m, "Output: HDMI, "); + break; + case INTEL_OUTPUT_DISPLAYPORT: + seq_puts(m, "Output: DP, "); + break; + default: + seq_puts(m, "Output: Others (id"); + seq_put_decimal_ull(m, '=', + intel_encoder->type); + seq_puts(m, "), "); + } + } + + if (intel_crtc->config->has_drrs) { + struct intel_panel *panel; + + panel = &drrs->dp->attached_connector->panel; + /* DRRS Supported */ + seq_puts(m, + "DRRS Supported: Yes (Seamless), "); + if (drrs->refresh_rate_type == DRRS_HIGH_RR) { + seq_puts(m, + "DRRS_State: DRRS_HIGH_RR, "); + vrefresh = panel->fixed_mode->vrefresh; + } else if (drrs->refresh_rate_type == + DRRS_LOW_RR) { + seq_puts(m, + "DRRS_State: DRRS_LOW_RR, "); + vrefresh = + panel->downclock_mode->vrefresh; + } else { + seq_puts(m, "DRRS_State: Unknown"); + seq_put_decimal_ull(m, '(', + drrs->refresh_rate_type); + seq_puts(m, "), "); + } + seq_puts(m, "Vrefresh:"); + seq_put_decimal_ull(m, ' ', vrefresh); + + } else { + /* DRRS not supported. Print the VBT parameter*/ + seq_puts(m, "DRRS Supported : No, "); + if (dev_priv->vbt.drrs_type == + STATIC_DRRS_SUPPORT) { + seq_puts(m, + "VBT DRRS_type: Static"); + } else if (dev_priv->vbt.drrs_type == + SEAMLESS_DRRS_SUPPORT) { + seq_puts(m, + "VBT DRRS_type: Seamless"); + } else if (dev_priv->vbt.drrs_type == + DRRS_NOT_SUPPORTED) { + seq_puts(m, "VBT DRRS_type: None"); + } + } + seq_puts(m, "\n"); + } + } + + if (!active_crtc_cnt) + seq_puts(m, "No active crtc found\n"); + + return 0; +} + struct pipe_crc_info { const char *name; struct drm_device *dev; @@ -4433,6 +4525,7 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_dp_mst_info", i915_dp_mst_info, 0}, {"i915_wa_registers", i915_wa_registers, 0}, {"i915_ddb_info", i915_ddb_info, 0}, + {"i915_drrs_status", i915_drrs_status, 0}, }; #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)