[3/4] drm/i915: Move current pll config to shared global state

Commit Message

Ander Conselvan de Oliveira Jan. 29, 2015, 2:55 p.m. UTC

This patch adds a display_state pointer to drm_i915_private and moves
the current pll config into it.

Signed-off-by: Ander Conselvan de Oliveira <[e-mail]>
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 15 ++++---
 drivers/gpu/drm/i915/i915_drv.h      |  4 +-
 drivers/gpu/drm/i915/intel_ddi.c     | 13 ++++--
 drivers/gpu/drm/i915/intel_display.c | 86 +++++++++++++++++++++++++-----------
 4 files changed, 79 insertions(+), 39 deletions(-)

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3b332a4..eb18a99 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2765,17 +2765,20 @@  static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 	drm_modeset_lock_all(dev);
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+		struct intel_shared_dpll_config *pll_config;
+
+		pll_config = &dev_priv->display_state->shared_dpll[i];
 
 		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
 		seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
-			   pll->config.crtc_mask, pll->active, yesno(pll->on));
+			   pll_config->crtc_mask, pll->active, yesno(pll->on));
 		seq_printf(m, " tracked hardware state:\n");
-		seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
+		seq_printf(m, " dpll:    0x%08x\n", pll_config->hw_state.dpll);
 		seq_printf(m, " dpll_md: 0x%08x\n",
-			   pll->config.hw_state.dpll_md);
-		seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
-		seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
-		seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
+			   pll_config->hw_state.dpll_md);
+		seq_printf(m, " fp0:     0x%08x\n", pll_config->hw_state.fp0);
+		seq_printf(m, " fp1:     0x%08x\n", pll_config->hw_state.fp1);
+		seq_printf(m, " wrpll:   0x%08x\n", pll_config->hw_state.wrpll);
 	}
 	drm_modeset_unlock_all(dev);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 862edc4..132eb7b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -296,8 +296,6 @@  struct intel_shared_dpll_config {
 };
 
 struct intel_shared_dpll {
-	struct intel_shared_dpll_config config;
-
 	int active; /* count of number of active CRTCs (i.e. DPMS on) */
 	bool on; /* is the PLL actually active? Disabled during modeset */
 	const char *name;
@@ -1784,6 +1782,8 @@  struct drm_i915_private {
 	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
 #endif
 
+	struct intel_atomic_state *display_state;
+
 	int num_shared_dpll;
 	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
 	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1cd541f..ff2197c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1747,7 +1747,10 @@  int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll)
 {
-	I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
+	struct intel_shared_dpll_config *pll_config =
+		&dev_priv->display_state->shared_dpll[pll->id];
+
+	I915_WRITE(WRPLL_CTL(pll->id), pll_config->hw_state.wrpll);
 	POSTING_READ(WRPLL_CTL(pll->id));
 	udelay(20);
 }
@@ -1836,6 +1839,8 @@  static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 	uint32_t val;
 	unsigned int dpll;
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
+	struct intel_shared_dpll_config *pll_config =
+		&dev_priv->display_state->shared_dpll[pll->id];
 
 	/* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
 	dpll = pll->id + 1;
@@ -1844,13 +1849,13 @@  static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 
 	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
 		 DPLL_CRTL1_LINK_RATE_MASK(dpll));
-	val |= pll->config.hw_state.ctrl1 << (dpll * 6);
+	val |= pll_config->hw_state.ctrl1 << (dpll * 6);
 
 	I915_WRITE(DPLL_CTRL1, val);
 	POSTING_READ(DPLL_CTRL1);
 
-	I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
-	I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
+	I915_WRITE(regs[pll->id].cfgcr1, pll_config->hw_state.cfgcr1);
+	I915_WRITE(regs[pll->id].cfgcr2, pll_config->hw_state.cfgcr2);
 	POSTING_READ(regs[pll->id].cfgcr1);
 	POSTING_READ(regs[pll->id].cfgcr2);
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 159e6c8..fecffbb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1778,11 +1778,13 @@  static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+	struct intel_shared_dpll_config *pll_config =
+		&dev_priv->display_state->shared_dpll[pll->id];
 
 	if (WARN_ON(pll == NULL))
 		return;
 
-	WARN_ON(!pll->config.crtc_mask);
+	WARN_ON(!pll_config->crtc_mask);
 	if (pll->active == 0) {
 		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
 		WARN_ON(pll->on);
@@ -1805,11 +1807,13 @@  static void intel_enable_shared_dpll(struct intel_crtc *crtc)
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+	struct intel_shared_dpll_config *pll_config =
+		&dev_priv->display_state->shared_dpll[pll->id];
 
 	if (WARN_ON(pll == NULL))
 		return;
 
-	if (WARN_ON(pll->config.crtc_mask == 0))
+	if (WARN_ON(pll_config->crtc_mask == 0))
 		return;
 
 	DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
@@ -1835,13 +1839,15 @@  static void intel_disable_shared_dpll(struct intel_crtc *crtc)
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+	struct intel_shared_dpll_config *pll_config =
+		&dev_priv->display_state->shared_dpll[pll->id];
 
 	/* PCH only available on ILK+ */
 	BUG_ON(INTEL_INFO(dev)->gen < 5);
 	if (WARN_ON(pll == NULL))
 	       return;
 
-	if (WARN_ON(pll->config.crtc_mask == 0))
+	if (WARN_ON(pll_config->crtc_mask == 0))
 		return;
 
 	DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
@@ -3871,18 +3877,21 @@  static void lpt_pch_enable(struct drm_crtc *crtc)
 
 void intel_put_shared_dpll(struct intel_crtc *crtc)
 {
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
+	struct intel_shared_dpll_config *pll_config =
+		&dev_priv->display_state->shared_dpll[pll->id];
 
 	if (pll == NULL)
 		return;
 
-	if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
+	if (!(pll_config->crtc_mask & (1 << crtc->pipe))) {
 		WARN(1, "bad %s crtc mask\n", pll->name);
 		return;
 	}
 
-	pll->config.crtc_mask &= ~(1 << crtc->pipe);
-	if (pll->config.crtc_mask == 0) {
+	pll_config->crtc_mask &= ~(1 << crtc->pipe);
+	if (pll_config->crtc_mask == 0) {
 		WARN_ON(pll->on);
 		WARN_ON(pll->active);
 	}
@@ -3966,14 +3975,16 @@  static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
 					  struct intel_atomic_state *state,
 					  unsigned clear_pipes)
 {
-	struct intel_shared_dpll *pll;
+	struct intel_shared_dpll_config *pll_config;
 	enum intel_dpll_id i;
 
+	/* FIXME: convert this to a simple memdup */
+
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
-		pll = &dev_priv->shared_dplls[i];
+		pll_config = &dev_priv->display_state->shared_dpll[i];
 
-		memcpy(&state->shared_dpll[i], &pll->config,
-		       sizeof pll->config);
+		memcpy(&state->shared_dpll[i], pll_config,
+		       sizeof *pll_config);
 		state->shared_dpll[i].crtc_mask &= ~clear_pipes;
 	}
 
@@ -3983,12 +3994,14 @@  static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv,
 				     struct intel_atomic_state *state)
 {
-	struct intel_shared_dpll *pll;
+	struct intel_shared_dpll_config *pll_config;
 	enum intel_dpll_id i;
 
+	/* FIXME: convert this to a poiner swap */
+
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
-		pll = &dev_priv->shared_dplls[i];
-		pll->config = state->shared_dpll[i];
+		pll_config = &dev_priv->display_state->shared_dpll[i];
+		*pll_config = state->shared_dpll[i];
 	}
 }
 
@@ -10864,6 +10877,8 @@  check_shared_dpll_state(struct drm_device *dev)
 
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+		struct intel_shared_dpll_config *pll_config =
+			&dev_priv->display_state->shared_dpll[pll->id];
 		int enabled_crtcs = 0, active_crtcs = 0;
 		bool active;
 
@@ -10873,9 +10888,9 @@  check_shared_dpll_state(struct drm_device *dev)
 
 		active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
 
-		I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
+		I915_STATE_WARN(pll->active > hweight32(pll_config->crtc_mask),
 		     "more active pll users than references: %i vs %i\n",
-		     pll->active, hweight32(pll->config.crtc_mask));
+		     pll->active, hweight32(pll_config->crtc_mask));
 		I915_STATE_WARN(pll->active && !pll->on,
 		     "pll in active use but not on in sw tracking\n");
 		I915_STATE_WARN(pll->on && !pll->active,
@@ -10893,11 +10908,11 @@  check_shared_dpll_state(struct drm_device *dev)
 		I915_STATE_WARN(pll->active != active_crtcs,
 		     "pll active crtcs mismatch (expected %i, found %i)\n",
 		     pll->active, active_crtcs);
-		I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
+		I915_STATE_WARN(hweight32(pll_config->crtc_mask) != enabled_crtcs,
 		     "pll enabled crtcs mismatch (expected %i, found %i)\n",
-		     hweight32(pll->config.crtc_mask), enabled_crtcs);
+		     hweight32(pll_config->crtc_mask), enabled_crtcs);
 
-		I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
+		I915_STATE_WARN(pll->on && memcmp(&pll_config->hw_state, &dpll_hw_state,
 				       sizeof(dpll_hw_state)),
 		     "pll hw state mismatch\n");
 	}
@@ -11675,17 +11690,23 @@  static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
 				  struct intel_shared_dpll *pll)
 {
-	I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
-	I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
+	struct intel_shared_dpll_config *pll_config =
+		&dev_priv->display_state->shared_dpll[pll->id];
+
+	I915_WRITE(PCH_FP0(pll->id), pll_config->hw_state.fp0);
+	I915_WRITE(PCH_FP1(pll->id), pll_config->hw_state.fp1);
 }
 
 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll)
 {
+	struct intel_shared_dpll_config *pll_config =
+		&dev_priv->display_state->shared_dpll[pll->id];
+
 	/* PCH refclock must be enabled first */
 	ibx_assert_pch_refclk_enabled(dev_priv);
 
-	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
+	I915_WRITE(PCH_DPLL(pll->id), pll_config->hw_state.dpll);
 
 	/* Wait for the clocks to stabilize. */
 	POSTING_READ(PCH_DPLL(pll->id));
@@ -11696,7 +11717,7 @@  static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
 	 *
 	 * So write it again.
 	 */
-	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
+	I915_WRITE(PCH_DPLL(pll->id), pll_config->hw_state.dpll);
 	POSTING_READ(PCH_DPLL(pll->id));
 	udelay(200);
 }
@@ -13139,6 +13160,13 @@  void intel_modeset_init(struct drm_device *dev)
 	enum pipe pipe;
 	struct intel_crtc *crtc;
 
+	dev_priv->display_state = kzalloc(sizeof *dev_priv->display_state,
+					  GFP_KERNEL);
+	if (!dev_priv->display_state) {
+		DRM_DEBUG_KMS("Failed to allocate display state.\n");
+		return;
+	}
+
 	drm_mode_config_init(dev);
 
 	dev->mode_config.min_width = 0;
@@ -13509,22 +13537,24 @@  static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
+		struct intel_shared_dpll_config *pll_config =
+			&dev_priv->display_state->shared_dpll[pll->id];
 
 		pll->on = pll->get_hw_state(dev_priv, pll,
-					    &pll->config.hw_state);
+					    &pll_config->hw_state);
 		pll->active = 0;
-		pll->config.crtc_mask = 0;
+		pll_config->crtc_mask = 0;
 		for_each_intel_crtc(dev, crtc) {
 			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
 				pll->active++;
-				pll->config.crtc_mask |= 1 << crtc->pipe;
+				pll_config->crtc_mask |= 1 << crtc->pipe;
 			}
 		}
 
 		DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
-			      pll->name, pll->config.crtc_mask, pll->on);
+			      pll->name, pll_config->crtc_mask, pll->on);
 
-		if (pll->config.crtc_mask)
+		if (pll_config->crtc_mask)
 			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
 	}
 
@@ -13749,6 +13779,8 @@  void intel_modeset_cleanup(struct drm_device *dev)
 	mutex_lock(&dev->struct_mutex);
 	intel_cleanup_gt_powersave(dev);
 	mutex_unlock(&dev->struct_mutex);
+
+	kfree(dev_priv->display_state);
 }
 
 /*