| Message ID | 1423510402-12605-5-git-send-email-damien.lespiau@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 09/02/2015 19:33, Damien Lespiau wrote: > WaDisableAsyncFlipPerfMode isn't listed for SKL and > INSTPM_FORCE_ORDERING is MBZ so let's make a gen9 specific render init > function. > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index d05f3bc..fe25ced 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1149,6 +1149,17 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring) > return init_workarounds_ring(ring); > } > > +static int gen9_init_render_ring(struct intel_engine_cs *ring) > +{ > + int ret; > + > + ret = gen8_init_common_ring(ring); > + if (ret) > + return ret; > + > + return init_workarounds_ring(ring); > +} > + > static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, > struct intel_context *ctx, > u64 offset, unsigned flags) > @@ -1408,7 +1419,10 @@ static int logical_render_ring_init(struct drm_device *dev) > if (HAS_L3_DPF(dev)) > ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; > > - ring->init_hw = gen8_init_render_ring; > + if (INTEL_INFO(dev)->gen >= 9) > + ring->init_hw = gen9_init_render_ring; > + else > + ring->init_hw = gen8_init_render_ring; > ring->init_context = gen8_init_rcs_context; > ring->cleanup = intel_fini_pipe_control; > ring->get_seqno = gen8_get_seqno; >
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d05f3bc..fe25ced 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1149,6 +1149,17 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring) return init_workarounds_ring(ring); } +static int gen9_init_render_ring(struct intel_engine_cs *ring) +{ + int ret; + + ret = gen8_init_common_ring(ring); + if (ret) + return ret; + + return init_workarounds_ring(ring); +} + static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, struct intel_context *ctx, u64 offset, unsigned flags) @@ -1408,7 +1419,10 @@ static int logical_render_ring_init(struct drm_device *dev) if (HAS_L3_DPF(dev)) ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; - ring->init_hw = gen8_init_render_ring; + if (INTEL_INFO(dev)->gen >= 9) + ring->init_hw = gen9_init_render_ring; + else + ring->init_hw = gen8_init_render_ring; ring->init_context = gen8_init_rcs_context; ring->cleanup = intel_fini_pipe_control; ring->get_seqno = gen8_get_seqno;
WaDisableAsyncFlipPerfMode isn't listed for SKL and INSTPM_FORCE_ORDERING is MBZ so let's make a gen9 specific render init function. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)