| Message ID | 1423658616-2298-1-git-send-email-ramalingam.c@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, This is preparation patch for "[PATCH] drm/i915/bdw: Add support for DRRS to switch RR". My bad that I have misplaced this in the thread. On Wednesday 11 February 2015 06:13 PM, Ramalingam C wrote: > Till Gen 7 we have two sets of M_N registers, but Gen 8 onwards > we have only one M_N register set. To support DRRS on both scenarios > a input parameter to intel_dp_set_m_n is added. > > In case of DRRS, When platform provides two set of M_N registers for dp, > we can program them with two different dividers and switch between them. > But when only one such register set is provided, we have to program > the required divider M_N value on that registers itself. > > Two enum members M1_N1 and M2_N2 are defined to represent the above > scenarios. > > M1_N1 : Program dp_m_n on M1_N1 registers > dp_m2_n2 on M2_N2 registers (If supported) > > M2_N2 : Program dp_m2_n2 on M1_N1 registers > M2_N2 registers are not supported > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++------- > drivers/gpu/drm/i915/intel_drv.h | 22 +++++++++++++++++++++- > 2 files changed, 44 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 3fe9598..ced049a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4316,7 +4316,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) > intel_prepare_shared_dpll(intel_crtc); > > if (intel_crtc->config->has_dp_encoder) > - intel_dp_set_m_n(intel_crtc); > + intel_dp_set_m_n(intel_crtc, M1_N1); > > intel_set_pipe_timings(intel_crtc); > > @@ -4424,7 +4424,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > intel_enable_shared_dpll(intel_crtc); > > if (intel_crtc->config->has_dp_encoder) > - intel_dp_set_m_n(intel_crtc); > + intel_dp_set_m_n(intel_crtc, M1_N1); > > intel_set_pipe_timings(intel_crtc); > > @@ -5038,7 +5038,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) > } > > if (intel_crtc->config->has_dp_encoder) > - intel_dp_set_m_n(intel_crtc); > + intel_dp_set_m_n(intel_crtc, M1_N1); > > intel_set_pipe_timings(intel_crtc); > > @@ -5114,7 +5114,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) > i9xx_set_pll_dividers(intel_crtc); > > if (intel_crtc->config->has_dp_encoder) > - intel_dp_set_m_n(intel_crtc); > + intel_dp_set_m_n(intel_crtc, M1_N1); > > intel_set_pipe_timings(intel_crtc); > > @@ -5889,13 +5889,29 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > } > } > > -void intel_dp_set_m_n(struct intel_crtc *crtc) > +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) > { > + struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; > + > + if (m_n == M1_N1) { > + dp_m_n = &crtc->config->dp_m_n; > + dp_m2_n2 = &crtc->config->dp_m2_n2; > + } else if (m_n == M2_N2) { > + > + /* > + * M2_N2 registers are not supported. Hence m2_n2 divider value > + * needs to be programmed into M1_N1. > + */ > + dp_m_n = &crtc->config->dp_m2_n2; > + } else { > + DRM_ERROR("Unsupported divider value\n"); > + return; > + } > + > if (crtc->config->has_pch_encoder) > intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); > else > - intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n, > - &crtc->config->dp_m2_n2); > + intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); > } > > static void vlv_update_pll(struct intel_crtc *crtc, > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 76b3c20..e05de19 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -593,6 +593,26 @@ struct intel_hdmi { > struct intel_dp_mst_encoder; > #define DP_MAX_DOWNSTREAM_PORTS 0x10 > > +/* > + * enum link_m_n_set: > + * When platform provides two set of M_N registers for dp, we can > + * program them and switch between them incase of DRRS. > + * But When only one such register is provided, we have to program the > + * required divider value on that registers itself based on the DRRS state. > + * > + * M1_N1 : Program dp_m_n on M1_N1 registers > + * dp_m2_n2 on M2_N2 registers (If supported) > + * > + * M2_N2 : Program dp_m2_n2 on M1_N1 registers > + * M2_N2 registers are not supported > + */ > + > +enum link_m_n_set { > + /* Sets the m1_n1 and m2_n2 */ > + M1_N1 = 0, > + M2_N2 > +}; > + > struct intel_dp { > uint32_t output_reg; > uint32_t aux_ch_ctl_reg; > @@ -994,7 +1014,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv); > void hsw_disable_pc8(struct drm_i915_private *dev_priv); > void intel_dp_get_m_n(struct intel_crtc *crtc, > struct intel_crtc_state *pipe_config); > -void intel_dp_set_m_n(struct intel_crtc *crtc); > +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); > int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); > void > ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3fe9598..ced049a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4316,7 +4316,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) intel_prepare_shared_dpll(intel_crtc); if (intel_crtc->config->has_dp_encoder) - intel_dp_set_m_n(intel_crtc); + intel_dp_set_m_n(intel_crtc, M1_N1); intel_set_pipe_timings(intel_crtc); @@ -4424,7 +4424,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_enable_shared_dpll(intel_crtc); if (intel_crtc->config->has_dp_encoder) - intel_dp_set_m_n(intel_crtc); + intel_dp_set_m_n(intel_crtc, M1_N1); intel_set_pipe_timings(intel_crtc); @@ -5038,7 +5038,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) } if (intel_crtc->config->has_dp_encoder) - intel_dp_set_m_n(intel_crtc); + intel_dp_set_m_n(intel_crtc, M1_N1); intel_set_pipe_timings(intel_crtc); @@ -5114,7 +5114,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) i9xx_set_pll_dividers(intel_crtc); if (intel_crtc->config->has_dp_encoder) - intel_dp_set_m_n(intel_crtc); + intel_dp_set_m_n(intel_crtc, M1_N1); intel_set_pipe_timings(intel_crtc); @@ -5889,13 +5889,29 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, } } -void intel_dp_set_m_n(struct intel_crtc *crtc) +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) { + struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; + + if (m_n == M1_N1) { + dp_m_n = &crtc->config->dp_m_n; + dp_m2_n2 = &crtc->config->dp_m2_n2; + } else if (m_n == M2_N2) { + + /* + * M2_N2 registers are not supported. Hence m2_n2 divider value + * needs to be programmed into M1_N1. + */ + dp_m_n = &crtc->config->dp_m2_n2; + } else { + DRM_ERROR("Unsupported divider value\n"); + return; + } + if (crtc->config->has_pch_encoder) intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); else - intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n, - &crtc->config->dp_m2_n2); + intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); } static void vlv_update_pll(struct intel_crtc *crtc, diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 76b3c20..e05de19 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -593,6 +593,26 @@ struct intel_hdmi { struct intel_dp_mst_encoder; #define DP_MAX_DOWNSTREAM_PORTS 0x10 +/* + * enum link_m_n_set: + * When platform provides two set of M_N registers for dp, we can + * program them and switch between them incase of DRRS. + * But When only one such register is provided, we have to program the + * required divider value on that registers itself based on the DRRS state. + * + * M1_N1 : Program dp_m_n on M1_N1 registers + * dp_m2_n2 on M2_N2 registers (If supported) + * + * M2_N2 : Program dp_m2_n2 on M1_N1 registers + * M2_N2 registers are not supported + */ + +enum link_m_n_set { + /* Sets the m1_n1 and m2_n2 */ + M1_N1 = 0, + M2_N2 +}; + struct intel_dp { uint32_t output_reg; uint32_t aux_ch_ctl_reg; @@ -994,7 +1014,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv); void hsw_disable_pc8(struct drm_i915_private *dev_priv); void intel_dp_get_m_n(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config); -void intel_dp_set_m_n(struct intel_crtc *crtc); +void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
Till Gen 7 we have two sets of M_N registers, but Gen 8 onwards we have only one M_N register set. To support DRRS on both scenarios a input parameter to intel_dp_set_m_n is added. In case of DRRS, When platform provides two set of M_N registers for dp, we can program them with two different dividers and switch between them. But when only one such register set is provided, we have to program the required divider M_N value on that registers itself. Two enum members M1_N1 and M2_N2 are defined to represent the above scenarios. M1_N1 : Program dp_m_n on M1_N1 registers dp_m2_n2 on M2_N2 registers (If supported) M2_N2 : Program dp_m2_n2 on M1_N1 registers M2_N2 registers are not supported Signed-off-by: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++------- drivers/gpu/drm/i915/intel_drv.h | 22 +++++++++++++++++++++- 2 files changed, 44 insertions(+), 8 deletions(-)