From patchwork Wed Feb 18 14:01:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: akash.goel@intel.com X-Patchwork-Id: 5844231 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 920859F380 for ; Wed, 18 Feb 2015 13:56:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 776BC201FE for ; Wed, 18 Feb 2015 13:56:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8485C201DD for ; Wed, 18 Feb 2015 13:55:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F0ECD6E4A3; Wed, 18 Feb 2015 05:55:58 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E1E76E4A3 for ; Wed, 18 Feb 2015 05:55:55 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 18 Feb 2015 05:50:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,602,1418112000"; d="scan'208";a="668078066" Received: from akashgoe-desktop.iind.intel.com ([10.223.82.76]) by fmsmga001.fm.intel.com with ESMTP; 18 Feb 2015 05:55:52 -0800 From: akash.goel@intel.com To: intel-gfx@lists.freedesktop.org Date: Wed, 18 Feb 2015 19:31:17 +0530 Message-Id: <1424268078-14541-7-git-send-email-akash.goel@intel.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1424268078-14541-1-git-send-email-akash.goel@intel.com> References: <1424268078-14541-1-git-send-email-akash.goel@intel.com> Cc: ankitprasad.r.sharma@intel.com, Akash Goel Subject: [Intel-gfx] [PATCH v2 5/5] drm/i915/skl: Updated the gen9_enable_rps function X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Akash Goel On SKL, GT frequency is programmed in units of 16.66 MHZ units compared to 50 MHZ for older platforms. Also the time value specified for Up/Down EI & Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28 us for older platforms. So updated the gen9_enable_rps function as per that. v2: Updated to use new macro GT_INTERVAL_FROM_US Signed-off-by: Akash Goel Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/intel_pm.c | 41 ++++++++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e08a710..6532060 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4035,27 +4035,50 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) static void gen9_enable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + u32 threshold_up, threshold_down; /* in % */ + u32 ei_up, ei_down; intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); gen6_init_rps_frequencies(dev); - I915_WRITE(GEN6_RPNSWREQ, 0xc800000); - I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000); + /* Program defaults and thresholds for RPS*/ + I915_WRITE(GEN6_RPNSWREQ, + GEN9_FREQUENCY(dev_priv->rps.rp1_freq * GEN9_FREQ_SCALER)); + I915_WRITE(GEN6_RC_VIDEO_FREQ, + GEN9_FREQUENCY(dev_priv->rps.rp1_freq * GEN9_FREQ_SCALER)); + + ei_up = 84480; /* 84.48ms */ + ei_down = 448000; + threshold_up = 90; + threshold_down = 70; + + I915_WRITE(GEN6_RP_UP_EI, + GT_INTERVAL_FROM_US(ei_up)); + I915_WRITE(GEN6_RP_UP_THRESHOLD, + GT_INTERVAL_FROM_US((ei_up * threshold_up / 100))); + + I915_WRITE(GEN6_RP_DOWN_EI, + GT_INTERVAL_FROM_US(ei_down)); + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, + GT_INTERVAL_FROM_US((ei_down * threshold_down / 100))); + + /* 1 second timeout*/ + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, GT_INTERVAL_FROM_US(1000000)); + + I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, + (dev_priv->rps.max_freq_softlimit * GEN9_FREQ_SCALER) << 23 | + (dev_priv->rps.min_freq_softlimit * GEN9_FREQ_SCALER) << 14); - I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); - I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000); - I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808); - I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08); - I915_WRITE(GEN6_RP_UP_EI, 0x101d0); - I915_WRITE(GEN6_RP_DOWN_EI, 0x55730); I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); - I915_WRITE(GEN6_PMINTRMSK, 0x6); I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO | GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX | GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_AVG); + dev_priv->rps.power = HIGH_POWER; /* force a reset */ + gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); + gen6_enable_rps_interrupts(dev); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);