From patchwork Thu Feb 26 15:31:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: deepak.s@linux.intel.com X-Patchwork-Id: 5894171 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8213F9F269 for ; Thu, 26 Feb 2015 15:35:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A00C7202E9 for ; Thu, 26 Feb 2015 15:35:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B76A2202A1 for ; Thu, 26 Feb 2015 15:35:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 338886E218; Thu, 26 Feb 2015 07:35:09 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E3BE6E218 for ; Thu, 26 Feb 2015 07:35:08 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 26 Feb 2015 07:35:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,653,1418112000"; d="scan'208";a="672104561" Received: from deepu.iind.intel.com ([10.223.82.32]) by fmsmga001.fm.intel.com with ESMTP; 26 Feb 2015 07:35:05 -0800 From: deepak.s@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 26 Feb 2015 21:01:52 +0530 Message-Id: <1424964712-16131-1-git-send-email-deepak.s@linux.intel.com> X-Mailer: git-send-email 1.9.1 Cc: "Satyanantha, Rama Gopal M" Subject: [Intel-gfx] [RFC] drm/i915: Framebuffers need not be limited to 256MB on gen8+. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Deepak S The restriction of pinningFramebuffer to first 256MB is removed from gen8+. Removing the restriction so that FB can be pinned in any space within GTT/PPGTT. Also, for gen8+ no need to use pin_mappable for Framebuffer & also we do not take fence as Framebuffer compression is not enabled. Signed-off-by: Satyanantha, Rama Gopal M Signed-off-by: Deepak S --- drivers/gpu/drm/i915/i915_gem.c | 9 +++++++-- drivers/gpu/drm/i915/intel_display.c | 11 +++++++---- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 77a7315..c9f5b06 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3941,6 +3941,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, struct intel_engine_cs *pipelined) { u32 old_read_domains, old_write_domain; + struct drm_device *dev = obj->base.dev; bool was_pin_display; int ret; @@ -3972,9 +3973,13 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, /* As the user may map the buffer once pinned in the display plane * (e.g. libkms for the bootup splash), we have to ensure that we - * always use map_and_fenceable for all scanout buffers. + * always use map_and_fenceable for all scanout buffers. No need + * of map_fenceable for >= gen8 */ - ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); + if ((INTEL_INFO(dev)->gen >= 8)) + ret = i915_gem_obj_ggtt_pin(obj, alignment, 0); + else + ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); if (ret) goto err_unpin_display; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index fad5f76..d3067be 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2267,11 +2267,14 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, /* Install a fence for tiled scan-out. Pre-i965 always needs a * fence, whereas 965+ only requires a fence if using * framebuffer compression. For simplicity, we always install - * a fence as the cost is not that onerous. + * a fence as the cost is not that onerous. Fence is only required + * for gen 7 & below */ - ret = i915_gem_object_get_fence(obj); - if (ret) - goto err_unpin; + if ((INTEL_INFO(dev)->gen <= 7)) { + ret = i915_gem_object_get_fence(obj); + if (ret) + goto err_unpin; + } i915_gem_object_pin_fence(obj);