From patchwork Tue Mar 3 13:22:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 5922771 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4894E9F318 for ; Tue, 3 Mar 2015 13:23:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 64FA4202EC for ; Tue, 3 Mar 2015 13:23:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6B34C201EC for ; Tue, 3 Mar 2015 13:23:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D5E706E5BC; Tue, 3 Mar 2015 05:23:14 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E65F6E5BE for ; Tue, 3 Mar 2015 05:23:13 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 03 Mar 2015 05:20:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,681,1418112000"; d="scan'208";a="693259166" Received: from linux.intel.com ([10.23.219.25]) by orsmga002.jf.intel.com with ESMTP; 03 Mar 2015 05:23:06 -0800 Received: from localhost (aconselv-mobl3.fi.intel.com [10.237.72.152]) by linux.intel.com (Postfix) with ESMTP id DEC006A408D; Tue, 3 Mar 2015 05:22:46 -0800 (PST) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Tue, 3 Mar 2015 15:22:14 +0200 Message-Id: <1425388937-1247-21-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1425388937-1247-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1425388937-1247-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 20/23] drm/i915: Use atomic state in pipe_has_enabled_pch() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This function is called indirectly by intel_crtc_compute_config(), which needs to be converted to work only with an atomic state. --- I'm not sure what are the implications of ignoring intel_crtc->active in pipe_has_enabled_pch(). If we allow a config because the third pipe is enabled but not active, wouldn't we run into trouble when we tried to activate the crtc? Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 64751b6..518903e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3150,10 +3150,9 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc) FDI_FE_ERRC_ENABLE); } -static bool pipe_has_enabled_pch(struct intel_crtc *crtc) +static bool pipe_has_enabled_pch(struct intel_crtc_state *crtc_state) { - return crtc->base.state->enable && crtc->active && - crtc->config->has_pch_encoder; + return crtc_state->base.enable && crtc_state->has_pch_encoder; } static void ivb_modeset_global_resources(struct drm_atomic_state *state) @@ -3164,15 +3163,21 @@ static void ivb_modeset_global_resources(struct drm_atomic_state *state) to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); struct intel_crtc *pipe_C_crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); + struct intel_crtc_state *pipe_B_crtc_state, *pipe_C_crtc_state; uint32_t temp; + pipe_B_crtc_state = intel_atomic_get_crtc_state(state, pipe_B_crtc); + pipe_C_crtc_state = intel_atomic_get_crtc_state(state, pipe_C_crtc); + if (WARN_ON(IS_ERR(pipe_B_crtc_state) || IS_ERR(pipe_C_crtc_state))) + return; + /* * When everything is off disable fdi C so that we could enable fdi B * with all lanes. Note that we don't care about enabled pipes without * an enabled pch encoder. */ - if (!pipe_has_enabled_pch(pipe_B_crtc) && - !pipe_has_enabled_pch(pipe_C_crtc)) { + if (!pipe_has_enabled_pch(pipe_B_crtc_state) && + !pipe_has_enabled_pch(pipe_C_crtc_state)) { WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); @@ -5528,6 +5533,9 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *pipe_B_crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); + struct intel_crtc_state *pipe_B_crtc_state = + intel_atomic_get_crtc_state(pipe_config->base.state, + pipe_B_crtc); DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", pipe_name(pipe), pipe_config->fdi_lanes); @@ -5563,8 +5571,8 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, } return true; case PIPE_C: - if (!pipe_has_enabled_pch(pipe_B_crtc) || - pipe_B_crtc->config->fdi_lanes <= 2) { + if (!pipe_has_enabled_pch(pipe_B_crtc_state) || + pipe_B_crtc_state->fdi_lanes <= 2) { if (pipe_config->fdi_lanes > 2) { DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", pipe_name(pipe), pipe_config->fdi_lanes);