From patchwork Thu Mar 5 15:57:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: deepak.s@linux.intel.com X-Patchwork-Id: 5947241 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BCEA6BF440 for ; Thu, 5 Mar 2015 16:01:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 95C5820392 for ; Thu, 5 Mar 2015 16:01:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 80C9F2038F for ; Thu, 5 Mar 2015 16:01:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0FB5F6E389; Thu, 5 Mar 2015 08:01:12 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id DFEE16E389 for ; Thu, 5 Mar 2015 08:01:10 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 05 Mar 2015 07:55:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,347,1422950400"; d="scan'208";a="675644665" Received: from deepu.iind.intel.com ([10.223.82.32]) by fmsmga001.fm.intel.com with ESMTP; 05 Mar 2015 08:01:01 -0800 From: deepak.s@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 5 Mar 2015 21:27:59 +0530 Message-Id: <1425571079-3051-1-git-send-email-deepak.s@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <54EFDC3A.9010908@linux.intel.com> References: <54EFDC3A.9010908@linux.intel.com> Subject: [Intel-gfx] [PATCH v2] drm/i915: Modifying RC6 Promotion timer for Media workloads. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Deepak S In normal cases, RC6 promotion timer is 1700us/500us. This will result in more time spent in C1 state. For more residency in C6 in case of media workloads, this is changed to 250us. Not doing this for 3D workloads as too many C6-C0 transition delays can result in performance impact. v2: Extend GPU busy & idle detection framework for rc6 Promotion timer changes (Chris) Signed-off-by: Deepak S --- drivers/gpu/drm/i915/i915_gem.c | 10 +++++++++- drivers/gpu/drm/i915/intel_display.c | 3 ++- drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++++ 4 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3831cc0..85f8aa6 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2428,7 +2428,7 @@ int __i915_add_request(struct intel_engine_cs *ring, struct drm_i915_gem_request *request; struct intel_ringbuffer *ringbuf; u32 request_start; - int ret; + int ret, was_empty; request = ring->outstanding_lazy_request; if (WARN_ON(request == NULL)) @@ -2495,6 +2495,7 @@ int __i915_add_request(struct intel_engine_cs *ring, } request->emitted_jiffies = jiffies; + was_empty = list_empty(&ring->request_list); list_add_tail(&request->list, &ring->request_list); request->file_priv = NULL; @@ -2519,6 +2520,10 @@ int __i915_add_request(struct intel_engine_cs *ring, queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, round_jiffies_up_relative(HZ)); + + if ((ring->id == VCS) && was_empty) + vlv_media_promotion_timer_busy(dev_priv); + intel_mark_busy(dev_priv->dev); return 0; @@ -2802,6 +2807,9 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring) } WARN_ON(i915_verify_lists(ring->dev)); + + if (ring->id == VCS && list_empty(&ring->request_list)) + vlv_media_promotion_timer_idle(dev_priv); } bool diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 597c10b..5d121b4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9172,8 +9172,9 @@ void intel_mark_idle(struct drm_device *dev) intel_decrease_pllclock(crtc); } - if (INTEL_INFO(dev)->gen >= 6) + if (INTEL_INFO(dev)->gen >= 6) { gen6_rps_idle(dev->dev_private); + } out: intel_runtime_pm_put(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 2a6ec4b..f1a90b8 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1233,6 +1233,8 @@ void ironlake_teardown_rc6(struct drm_device *dev); void gen6_update_ring_freq(struct drm_device *dev); void gen6_rps_idle(struct drm_i915_private *dev_priv); void gen6_rps_boost(struct drm_i915_private *dev_priv); +void vlv_media_promotion_timer_idle(struct drm_i915_private *dev_priv); +void vlv_media_promotion_timer_busy(struct drm_i915_private *dev_priv); void ilk_wm_get_hw_state(struct drm_device *dev); void skl_wm_get_hw_state(struct drm_device *dev); void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e710b43..d23b60a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3961,6 +3961,33 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv) mutex_unlock(&dev_priv->rps.hw_lock); } +void vlv_media_promotion_timer_idle(struct drm_i915_private *dev_priv) +{ + struct drm_device *dev = dev_priv->dev; + + if (!IS_VALLEYVIEW(dev)) + return; + + if (IS_CHERRYVIEW(dev_priv->dev)) { + /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ + I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); + } else { + /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ + I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); + } +} + +void vlv_media_promotion_timer_busy(struct drm_i915_private *dev_priv) +{ + struct drm_device *dev = dev_priv->dev; + + if (!IS_VALLEYVIEW(dev)) + return; + + /* TO threshold set to 250 us ( 0xC3 * 1.28 us) */ + I915_WRITE(GEN6_RC6_THRESHOLD, 0xC3); +} + void intel_set_rps(struct drm_device *dev, u8 val) { if (IS_VALLEYVIEW(dev))