From patchwork Sun Mar 15 05:55:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chandra Konduru X-Patchwork-Id: 6012491 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D07819F2A9 for ; Sun, 15 Mar 2015 05:56:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D4717201CE for ; Sun, 15 Mar 2015 05:56:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E5E5820172 for ; Sun, 15 Mar 2015 05:56:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 03F856E4B4; Sat, 14 Mar 2015 22:56:51 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C7526E4A9 for ; Sat, 14 Mar 2015 22:56:39 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 14 Mar 2015 22:54:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,403,1422950400"; d="scan'208";a="665398830" Received: from cmkondur-desk2.fm.intel.com ([10.19.123.59]) by orsmga001.jf.intel.com with ESMTP; 14 Mar 2015 22:56:39 -0700 From: Chandra Konduru To: intel-gfx@lists.freedesktop.org Date: Sat, 14 Mar 2015 22:55:45 -0700 Message-Id: <1426398946-5900-21-git-send-email-chandra.konduru@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1426398946-5900-1-git-send-email-chandra.konduru@intel.com> References: <1426398946-5900-1-git-send-email-chandra.konduru@intel.com> Cc: ander.conselvan.de.oliveira@intel.com, daniel.vetter@intel.com Subject: [Intel-gfx] [PATCH 20/21] drm/i915: Enable skylake primary plane scaling using shared scalers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch enables skylake primary plane display scaling using shared scalers atomic desgin. Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/intel_display.c | 77 +++++++++++++++++++++++++++++++--- 1 file changed, 71 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8deebb7..d63be8e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2883,6 +2883,16 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, struct drm_i915_gem_object *obj; int pipe = intel_crtc->pipe; u32 plane_ctl, stride_div; + struct intel_crtc_state *crtc_state = intel_crtc->config; + struct intel_plane_state *plane_state; + int src_x = 0, src_y = 0, src_w = 0, src_h = 0; + int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; + int scaler_id = -1; + + plane_state = crtc->primary ? + to_intel_plane_state(crtc->primary->state) : NULL; + + skl_detach_scaler(crtc, crtc->primary); if (!intel_crtc->primary_enabled) { I915_WRITE(PLANE_CTL(pipe, 0), 0); @@ -2950,13 +2960,42 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc, stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], fb->pixel_format); + if (plane_state) { + scaler_id = plane_state->scaler_id; + src_x = plane_state->src.x1 >> 16; + src_y = plane_state->src.y1 >> 16; + src_w = drm_rect_width(&plane_state->src) >> 16; + src_h = drm_rect_height(&plane_state->src) >> 16; + dst_x = plane_state->dst.x1; + dst_y = plane_state->dst.y1; + dst_w = drm_rect_width(&plane_state->dst); + dst_h = drm_rect_height(&plane_state->dst); + } + I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); - I915_WRITE(PLANE_POS(pipe, 0), 0); + if (src_w && src_h && dst_w && dst_h && scaler_id >= 0) { + uint32_t ps_ctrl = 0; + + WARN_ON(x != src_x || y != src_y); + ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | + crtc_state->scaler_state.scalers[scaler_id].mode | + crtc_state->scaler_state.scalers[scaler_id].filter; + I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); + I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); + I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); + I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); + + I915_WRITE(PLANE_POS(pipe, 0), 0); + I915_WRITE(PLANE_SIZE(pipe, 0), ((src_h - 1) << 16) | (src_w - 1)); + } else { + I915_WRITE(PLANE_POS(pipe, 0), 0); + I915_WRITE(PLANE_SIZE(pipe, 0), + (intel_crtc->config->pipe_src_h - 1) << 16 | + (intel_crtc->config->pipe_src_w - 1)); + } + I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); - I915_WRITE(PLANE_SIZE(pipe, 0), - (intel_crtc->config->pipe_src_h - 1) << 16 | - (intel_crtc->config->pipe_src_w - 1)); I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div); I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); @@ -12561,19 +12600,33 @@ intel_check_primary_plane(struct drm_plane *plane, struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *crtc = state->base.crtc; struct intel_crtc *intel_crtc; + struct intel_crtc_state *crtc_state; struct drm_framebuffer *fb = state->base.fb; struct drm_rect *dest = &state->dst; struct drm_rect *src = &state->src; const struct drm_rect *clip = &state->clip; + struct intel_crtc_scaler_state *scaler_state; + int max_scale = DRM_PLANE_HELPER_NO_SCALING; + int min_scale = DRM_PLANE_HELPER_NO_SCALING; int ret; crtc = crtc ? crtc : plane->crtc; intel_crtc = to_intel_crtc(crtc); + crtc_state = state->base.state ? + intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; + scaler_state = crtc_state ? &crtc_state->scaler_state : NULL; + + if (INTEL_INFO(dev)->gen >= 9) { + if (scaler_state && scaler_state->num_scalers) { + min_scale = 1; + max_scale = (100 << 16) / scaler_state->scalers[0].min_hsr; + } + } ret = drm_plane_helper_check_update(plane, crtc, fb, src, dest, clip, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + min_scale, + max_scale, false, true, &state->visible); if (ret) return ret; @@ -12620,6 +12673,13 @@ intel_check_primary_plane(struct drm_plane *plane, intel_crtc->atomic.update_wm = true; } + if (INTEL_INFO(dev)->gen >= 9) { + ret = skl_update_scaler_users(intel_crtc, crtc_state, + to_intel_plane(plane), state); + if (ret) + return ret; + } + return 0; } @@ -12803,6 +12863,11 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, primary->can_scale = false; primary->max_downscale = 1; + if (INTEL_INFO(dev)->gen >= 9) { + primary->can_scale = true; + primary->max_downscale = 2; /* updated later */ + primary->get_colorkey = skl_get_colorkey; + } state->scaler_id = -1; primary->pipe = pipe; primary->plane = pipe;