From patchwork Wed Mar 25 23:21:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chandra Konduru X-Patchwork-Id: 6095961 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 442679F399 for ; Wed, 25 Mar 2015 23:22:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 67EEE20381 for ; Wed, 25 Mar 2015 23:21:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8877820357 for ; Wed, 25 Mar 2015 23:21:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C78AC6E956; Wed, 25 Mar 2015 16:21:57 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 54A9E6E956 for ; Wed, 25 Mar 2015 16:21:56 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 25 Mar 2015 16:21:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,467,1422950400"; d="scan'208";a="546392673" Received: from cmkondur-desk2.fm.intel.com ([10.19.123.59]) by orsmga003.jf.intel.com with ESMTP; 25 Mar 2015 16:21:55 -0700 From: Chandra Konduru To: intel-gfx@lists.freedesktop.org Date: Wed, 25 Mar 2015 16:21:19 -0700 Message-Id: <1427325679-29900-1-git-send-email-chandra.konduru@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1426896282-23215-8-git-send-email-chandra.konduru@intel.com> References: <1426896282-23215-8-git-send-email-chandra.konduru@intel.com> Cc: ander.conselvan.de.oliveira@intel.com, daniel.vetter@intel.com Subject: [Intel-gfx] [PATCH 07/21 v3] drm/i915: Helper function to update skylake scaling ratio. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Helper function updates supported scaling ratios based on cdclk and crtc clocks. v2: -update single copy of scaling ratios (Matt) v3: -min scaling ratio is limited by either display engine limit or clocks, it is not related to previous ratio (Matt, me) Signed-off-by: Chandra Konduru --- drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ec58f1d..29d46fc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4513,6 +4513,31 @@ static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) intel_wait_for_vblank(dev, other_active_crtc->pipe); } +static void skl_update_scaling_ratio(struct drm_device *dev, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t crtc_clock, cdclk; + struct intel_crtc_scaler_state *scaler_state; + + if (!crtc_state) + return; + + crtc_clock = (uint32_t) crtc_state->base.adjusted_mode.crtc_clock; + cdclk = (uint32_t) intel_ddi_get_cdclk_freq(dev_priv); + + if (!crtc_clock || !cdclk) + return; + + scaler_state = &crtc_state->scaler_state; + scaler_state->min_hsr = max((uint32_t)34, (crtc_clock * 100)/cdclk); + scaler_state->min_vsr = max((uint32_t)34, (crtc_clock * 100)/cdclk); + scaler_state->min_hvsr = max((uint32_t)12, (crtc_clock * 100)/cdclk); + + DRM_DEBUG_KMS("for crtc_state = %p crtc_clock = %d cdclk = %d\n", crtc_state, + crtc_clock, cdclk); +} + static void haswell_crtc_enable(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev;