From patchwork Mon Mar 30 21:00:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anuj Phogat X-Patchwork-Id: 6125341 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CB8949F2EC for ; Mon, 30 Mar 2015 21:01:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ED9C120429 for ; Mon, 30 Mar 2015 21:01:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1228E2041E for ; Mon, 30 Mar 2015 21:01:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55FE06E62F; Mon, 30 Mar 2015 14:01:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pa0-f48.google.com (mail-pa0-f48.google.com [209.85.220.48]) by gabe.freedesktop.org (Postfix) with ESMTP id A91B16E630 for ; Mon, 30 Mar 2015 14:01:11 -0700 (PDT) Received: by pactp5 with SMTP id tp5so11752871pac.1 for ; Mon, 30 Mar 2015 14:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=pcLrAVKpadmFmlJDYwFsfEgB5iysfNTTEWRrqP4dt3c=; b=gtI1AvxL3ZOJX2ENtlue5bq+2wIjqOqZwfEtiG6bkkvISfZDgNgiUIraWILz5eJSvJ IoUBuAQIAZjbD5tOW4TJ8rR8AG7oWvnmr5MOb0pETjUC/nB7zhqMh9slyS5IVa1MZcPj ENWH9yfwL8pv+ttV1lS03C4WGs3EwKqYjMOlcR8B0TXhH366w5y9pHnZIQoIh+gDvNCi 3Qnyeyeb7ydOZzsHtRG2gAqrC0CVf7IhMResva4v+amTAYH4hoZDX21vbPeTERbojerH rtsC65+KMOqGEiE3a/8/4EsQi99fBn3AP1B7v9jDpyQS5JxohE7gXRkamXCDLMXC+BJ6 mqdA== X-Received: by 10.68.69.47 with SMTP id b15mr9051070pbu.76.1427749271435; Mon, 30 Mar 2015 14:01:11 -0700 (PDT) Received: from carbon.ak.intel.com (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by mx.google.com with ESMTPSA id g9sm875640pdj.24.2015.03.30.14.01.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 30 Mar 2015 14:01:10 -0700 (PDT) From: Anuj Phogat To: Date: Mon, 30 Mar 2015 14:00:06 -0700 Message-Id: <1427749208-8961-4-git-send-email-anuj.phogat@gmail.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1427749208-8961-1-git-send-email-anuj.phogat@gmail.com> References: <1427749208-8961-1-git-send-email-anuj.phogat@gmail.com> Subject: [Intel-gfx] [PATCH 3/5] i965/skl: Set tile width and height for YF/YS tiling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP I'm still passing tiling=I915_TILING_Y in drm_intel_gem_bo_alloc_internal() in case of YF/YS tiling. Passing tiling=I915_TILING_{YF,YS} causes bo allocation failure. Any advice what's the right thing to do here? Signed-off-by: Anuj Phogat --- intel/intel_bufmgr_gem.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index af44ba5..7c50e26 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -803,6 +803,39 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, I915_TILING_NONE, 0); } +/* This function does tile height computations valid only for Yf/Ys tiled + * surfaces. + */ +static unsigned +drm_intel_gem_tile_height(unsigned bpp, uint32_t tiling) +{ + unsigned tile_height; + assert(tiling == I915_TILING_YF || tiling == I915_TILING_YS); + + switch (bpp) { + case 8: + tile_height = 64; + break; + case 16: + case 32: + tile_height = 32; + break; + case 64: + case 128: + tile_height = 16; + break; + default: + printf("Invalid bits per pixel in %s: bpp = %d\n", + __FUNCTION__, bpp); + return 0; + } + + if (tiling == I915_TILING_YS) + tile_height *= 4; + + return tile_height; +} + static drm_intel_bo * drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, int x, int y, int cpp, uint32_t *tiling_mode, @@ -838,7 +871,15 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, && tiling == I915_TILING_Y)) { height_alignment = 8; tile_width = 512; - } else if (tiling == I915_TILING_Y) + } else if (tiling == I915_TILING_YF || + tiling == I915_TILING_YS) { + unsigned bpp = cpp * 8; + unsigned aspect_ratio = + (bpp == 16 || bpp == 64) ? 2 : 1; + height_alignment = + drm_intel_gem_tile_height(bpp, tiling); + tile_width = height_alignment * cpp * aspect_ratio; + } else if (tiling == I915_TILING_Y){ height_alignment = 32; tile_width = 128; } @@ -855,6 +896,12 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, if (tiling == I915_TILING_NONE) stride = 0; + /* Use I915_TILING_Y in drm_intel_gem_bo_alloc_internal() in case of + * YF/YS tiling. + */ + tiling = (tiling == I915_TILING_YF || tiling == I915_TILING_YS) ? + I915_TILING_Y : tiling; + return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags, tiling, stride); }