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[1/2] drm/i915/vlv: save/restore the power context base reg

Message ID 1427923378-2116-1-git-send-email-jbarnes@virtuousgeek.org (mailing list archive)
State New, archived
Headers show

Commit Message

Jesse Barnes April 1, 2015, 9:22 p.m. UTC
Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
reg.  If it's unlocked, we can just restore the previous value, and if
it's locked (in case the BIOS re-programmed it for us) the write will be
ignored and we'll still have "did it move" sanity check in the PM code to
warn us if something is still amiss.

References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 ++
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 2 files changed, 3 insertions(+)

Comments

Jani Nikula April 2, 2015, 7:45 a.m. UTC | #1
On Thu, 02 Apr 2015, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
> reg.  If it's unlocked, we can just restore the previous value, and if
> it's locked (in case the BIOS re-programmed it for us) the write will be
> ignored and we'll still have "did it move" sanity check in the PM code to
> warn us if something is still amiss.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611

Both patches

Tested-by: Darren Hart <dvhart@linux.intel.com>
Cc: stable@vger.kernel.org


> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 2 ++
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index c1a3cdb5..4d6d6f0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1104,6 +1104,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>  	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
>  	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
> +	s->pcbr			= I915_READ(VLV_PCBR);
>  	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
>  
>  	/*
> @@ -1198,6 +1199,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>  	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
>  	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
> +	I915_WRITE(VLV_PCBR,			s->pcbr);
>  	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b13c552..f3ac683 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -994,6 +994,7 @@ struct vlv_s0ix_state {
>  	/* Display 2 CZ domain */
>  	u32 gu_ctl0;
>  	u32 gu_ctl1;
> +	u32 pcbr;
>  	u32 clock_gate_dis2;
>  };
>  
> -- 
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Imre Deak April 2, 2015, 7:49 a.m. UTC | #2
On Wed, 2015-04-01 at 14:22 -0700, Jesse Barnes wrote:
> Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
> reg.  If it's unlocked, we can just restore the previous value, and if
> it's locked (in case the BIOS re-programmed it for us) the write will be
> ignored and we'll still have "did it move" sanity check in the PM code to
> warn us if something is still amiss.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Yea, the BIOS is supposed to program this reg according to the Gunit
doc, but we can't have any guarantee anyway.. I guess this is a problem
only for S3, but I can't see any problem saving/restoring it also during
s0ix, so:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 2 ++
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index c1a3cdb5..4d6d6f0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1104,6 +1104,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>  	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
>  	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
> +	s->pcbr			= I915_READ(VLV_PCBR);
>  	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
>  
>  	/*
> @@ -1198,6 +1199,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>  	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>  	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
>  	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
> +	I915_WRITE(VLV_PCBR,			s->pcbr);
>  	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b13c552..f3ac683 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -994,6 +994,7 @@ struct vlv_s0ix_state {
>  	/* Display 2 CZ domain */
>  	u32 gu_ctl0;
>  	u32 gu_ctl1;
> +	u32 pcbr;
>  	u32 clock_gate_dis2;
>  };
>
deepak.s@linux.intel.com April 2, 2015, 10:23 a.m. UTC | #3
On Thursday 02 April 2015 02:52 AM, Jesse Barnes wrote:
> Some BIOSes (e.g. the one on the Minnowboard) don't save/restore this
> reg.  If it's unlocked, we can just restore the previous value, and if
> it's locked (in case the BIOS re-programmed it for us) the write will be
> ignored and we'll still have "did it move" sanity check in the PM code to
> warn us if something is still amiss.

Looks fine to me
Reviewed-by: Deepak S<deepak.s@linux.intel.com>

> References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>   drivers/gpu/drm/i915/i915_drv.c | 2 ++
>   drivers/gpu/drm/i915/i915_drv.h | 1 +
>   2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index c1a3cdb5..4d6d6f0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1104,6 +1104,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>   	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>   	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
>   	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
> +	s->pcbr			= I915_READ(VLV_PCBR);
>   	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
>   
>   	/*
> @@ -1198,6 +1199,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>   	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
>   	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
>   	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
> +	I915_WRITE(VLV_PCBR,			s->pcbr);
>   	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
>   }
>   
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b13c552..f3ac683 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -994,6 +994,7 @@ struct vlv_s0ix_state {
>   	/* Display 2 CZ domain */
>   	u32 gu_ctl0;
>   	u32 gu_ctl1;
> +	u32 pcbr;
>   	u32 clock_gate_dis2;
>   };
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c1a3cdb5..4d6d6f0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1104,6 +1104,7 @@  static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
 	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
 	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
+	s->pcbr			= I915_READ(VLV_PCBR);
 	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);
 
 	/*
@@ -1198,6 +1199,7 @@  static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
 	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
 	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
 	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
+	I915_WRITE(VLV_PCBR,			s->pcbr);
 	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b13c552..f3ac683 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -994,6 +994,7 @@  struct vlv_s0ix_state {
 	/* Display 2 CZ domain */
 	u32 gu_ctl0;
 	u32 gu_ctl1;
+	u32 pcbr;
 	u32 clock_gate_dis2;
 };