| Message ID | 1428655290-836-2-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Apr 10, 2015 at 02:11:30PM +0530, sagar.a.kamble@intel.com wrote: > From: Sagar Kamble <sagar.a.kamble@intel.com> > > When RC6 along with Render power gating is enabled, GPU hang > happens due to lack of synchronization between GTI and Render reset. > > Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c > Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> > > Conflicts: > drivers/gpu/drm/i915/intel_pm.c So, is this a hang that occurs at reset? Do you know if we can do better by disabling/enabling it around reset? > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 9975401..f080710 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev) > GEN6_RC_CTL_EI_MODE(1) | > rc6_mask); > > - /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ > + /* > + * 3b: Enable Coarse Power Gating only when RC6 is enabled. > + * WaDisableRenderPowerGating - Render PG need to be disabled with RC6. > + */ I don't see any WaDisableRenderPowerGating name in the wa databse, where does that name come from? > I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? > - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); > + GEN9_MEDIA_PG_ENABLE : 0); > > > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > -- > 1.8.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, Apr 10, 2015 at 02:11:30PM +0530, sagar.a.kamble@intel.com wrote: > From: Sagar Kamble <sagar.a.kamble@intel.com> > > When RC6 along with Render power gating is enabled, GPU hang > happens due to lack of synchronization between GTI and Render reset. Maybe, instead of reset here, say render being power gated? > Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c > Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> > > Conflicts: > drivers/gpu/drm/i915/intel_pm.c I have limited info about this, but it seems to fix something that has been characterized recently. There may be more dubious interactions to fix around this coarse power gating, RC6 entry and forcewake, but that's another story. So with the skl,bxt mention added: Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 9975401..f080710 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev) > GEN6_RC_CTL_EI_MODE(1) | > rc6_mask); > > - /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ > + /* > + * 3b: Enable Coarse Power Gating only when RC6 is enabled. > + * WaDisableRenderPowerGating - Render PG need to be disabled with RC6. > + */ WaDisableRenderPowerGating:skl,bxt > I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? > - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); > + GEN9_MEDIA_PG_ENABLE : 0); > > > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > -- > 1.8.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9975401..f080710 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev) GEN6_RC_CTL_EI_MODE(1) | rc6_mask); - /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ + /* + * 3b: Enable Coarse Power Gating only when RC6 is enabled. + * WaDisableRenderPowerGating - Render PG need to be disabled with RC6. + */ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); + GEN9_MEDIA_PG_ENABLE : 0); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);