diff mbox

[1/1] drm/i915: Disable Render power gating

Message ID 1428667354-22366-1-git-send-email-sagar.a.kamble@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

sagar.a.kamble@intel.com April 10, 2015, 12:02 p.m. UTC 
From: Sagar Kamble <sagar.a.kamble@intel.com>

When RC6 along with Render power gating is enabled, GPU hang
happens due to lack of synchronization between GTI and Render
power gating.

Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Comments

Daniel Vetter April 10, 2015, 2:16 p.m. UTC | #1 
On Fri, Apr 10, 2015 at 05:32:34PM +0530, sagar.a.kamble@intel.com wrote:
> From: Sagar Kamble <sagar.a.kamble@intel.com>
> 
> When RC6 along with Render power gating is enabled, GPU hang
> happens due to lack of synchronization between GTI and Render
> power gating.
> 
When resending patches please have a per-patch changelog here. And if the
patch is reviewed please also add all these tags when resending. Otherwise
the patch gets lost easily.

Merged the first one meanwhile, thanks.
-Daniel

> Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9975401..4dd8b41 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4350,9 +4350,12 @@ static void gen9_enable_rc6(struct drm_device *dev)
>  				   GEN6_RC_CTL_EI_MODE(1) |
>  				   rc6_mask);
>  
> -	/* 3b: Enable Coarse Power Gating only when RC6 is enabled */
> +	/*
> +	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> +	 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
> +	 */
>  	I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
> -			(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
> +			GEN9_MEDIA_PG_ENABLE : 0);
>  
>  
>  	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> -- 
> 1.8.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9975401..4dd8b41 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4350,9 +4350,12 @@  static void gen9_enable_rc6(struct drm_device *dev)
 				   GEN6_RC_CTL_EI_MODE(1) |
 				   rc6_mask);
 
-	/* 3b: Enable Coarse Power Gating only when RC6 is enabled */
+	/*
+	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
+	 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
+	 */
 	I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
-			(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
+			GEN9_MEDIA_PG_ENABLE : 0);
 
 
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);