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[13/14] drm/i915: Limit CHV max cdclk

Message ID 1429103244-3515-14-git-send-email-mika.kahola@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kahola April 15, 2015, 1:07 p.m. UTC 
Limit CHV maximum cdclk to 320MHz.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ville Syrjälä April 15, 2015, 7:19 p.m. UTC | #1 
On Wed, Apr 15, 2015 at 04:07:23PM +0300, Mika Kahola wrote:
> Limit CHV maximum cdclk to 320MHz.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 09f3518..d79421a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5239,7 +5239,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
>  		else
>  			dev_priv->max_cdclk_freq = 540000;
>  	} else if (IS_VALLEYVIEW(dev)) {
> -		dev_priv->max_cdclk_freq = 400000;
> +		dev_priv->max_cdclk_freq = IS_CHERRYVIEW(dev) ? 320000 : 400000;
>  	} else {
>  		/* otherwise assume cdclk is fixed */
>  		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 09f3518..d79421a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5239,7 +5239,7 @@  static void intel_update_max_cdclk(struct drm_device *dev)
 		else
 			dev_priv->max_cdclk_freq = 540000;
 	} else if (IS_VALLEYVIEW(dev)) {
-		dev_priv->max_cdclk_freq = 400000;
+		dev_priv->max_cdclk_freq = IS_CHERRYVIEW(dev) ? 320000 : 400000;
 	} else {
 		/* otherwise assume cdclk is fixed */
 		dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;