From patchwork Wed Apr 15 13:07:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mika Kahola X-Patchwork-Id: 6220681 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2454FBF4A7 for ; Wed, 15 Apr 2015 13:09:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3729F200FF for ; Wed, 15 Apr 2015 13:09:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3F78E202A1 for ; Wed, 15 Apr 2015 13:09:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BDF336E869; Wed, 15 Apr 2015 06:09:40 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id B71596E862 for ; Wed, 15 Apr 2015 06:09:34 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 15 Apr 2015 06:08:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,582,1422950400"; d="scan'208";a="714047388" Received: from sorvi.fi.intel.com ([10.237.72.165]) by orsmga002.jf.intel.com with ESMTP; 15 Apr 2015 06:08:14 -0700 From: Mika Kahola To: intel-gfx@lists.freedesktop.org Date: Wed, 15 Apr 2015 16:07:24 +0300 Message-Id: <1429103244-3515-15-git-send-email-mika.kahola@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1429103244-3515-1-git-send-email-mika.kahola@intel.com> References: <1429103244-3515-1-git-send-email-mika.kahola@intel.com> Subject: [Intel-gfx] [PATCH 14/14] drm/i915: Modeset global_pipes() update X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()' into one function 'intel_modeset_global_pipes()' v2: - we don't modify 'disable_pipes', so passing this as a pointer is removed (based on Ville's comment) - introduced a new function 'intel_calc_cdclk()' that combines routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()' v3: - Let's take a step back and not remove the routines 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()' from newly introduced routine 'intel_calc_cdclk()' (based on Ville's comment) v4: - Rebased to the latest Signed-off-by: Mika Kahola Reviewed-by: Ville Syrjälä Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/intel_display.c | 70 +++++++++++++++++------------------- 1 file changed, 32 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d79421a..f199faa 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5433,28 +5433,6 @@ static int intel_mode_max_pixclk(struct drm_atomic_state *state) return max_pixclk; } -static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, - unsigned *prepare_pipes) -{ - struct drm_i915_private *dev_priv = to_i915(state->dev); - struct intel_crtc *intel_crtc; - int max_pixclk = intel_mode_max_pixclk(state); - - if (max_pixclk < 0) - return max_pixclk; - - if (valleyview_calc_cdclk(dev_priv, max_pixclk) == - dev_priv->cdclk_freq) - return 0; - - /* disable/enable all currently active pipes while we change cdclk */ - for_each_intel_crtc(state->dev, intel_crtc) - if (intel_crtc->base.state->enable) - *prepare_pipes |= (1 << intel_crtc->pipe); - - return 0; -} - static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) { unsigned int credits, default_credits; @@ -9265,21 +9243,47 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) cdclk, dev_priv->cdclk_freq); } -static void haswell_modeset_global_pipes(struct drm_atomic_state *state, - unsigned *prepare_pipes) +static int intel_calc_cdclk(struct drm_device *dev, int max_pixclk) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int cdclk = 200000; + + if (IS_VALLEYVIEW(dev)) + cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); + else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) + cdclk = haswell_calc_cdclk(dev_priv, max_pixclk); + + return cdclk; +} + +static void intel_modeset_global_pipes(struct drm_atomic_state *state, + unsigned *prepare_pipes, + unsigned disable_pipes) { struct drm_device *dev = state->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc *crtc; - int max_pixel_rate = ilk_max_pixel_rate(dev_priv); + int max_pixclk; - if (haswell_calc_cdclk(dev_priv, max_pixel_rate) == dev_priv->cdclk_freq) + /* this modeset is valid only for VLV, HSW, and BDW */ + if (!IS_VALLEYVIEW(dev) && !IS_HASWELL(dev) && !IS_BROADWELL(dev)) + return; + + if (IS_VALLEYVIEW(dev)) + max_pixclk = intel_mode_max_pixclk(state); + else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) + max_pixclk = ilk_max_pixel_rate(dev_priv); + + if (intel_calc_cdclk(dev, max_pixclk) == dev_priv->cdclk_freq) return; /* disable/enable all currently active pipes while we change cdclk */ for_each_intel_crtc(dev, crtc) - if (crtc->base.enabled) + if (crtc->base.state->enable) *prepare_pipes |= 1 << crtc->pipe; + + /* may have added more to prepare_pipes than we should */ + *prepare_pipes &= ~disable_pipes; } static void haswell_modeset_global_resources(struct drm_atomic_state *state) @@ -12453,17 +12457,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, * mode set on this crtc. For other crtcs we need to use the * adjusted_mode bits in the crtc directly. */ - if (IS_VALLEYVIEW(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { - if (IS_VALLEYVIEW(dev)) - valleyview_modeset_global_pipes(state, &prepare_pipes); - else - haswell_modeset_global_pipes(state, &prepare_pipes); - if (ret) - goto done; - - /* may have added more to prepare_pipes than we should */ - prepare_pipes &= ~disable_pipes; - } + intel_modeset_global_pipes(state, &prepare_pipes, disable_pipes); ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes); if (ret)