| Message ID | 1430276784-7228-1-git-send-email-deepak.s@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepak.s@linux.intel.com wrote: > From: Deepak S <deepak.s@linux.intel.com> > > Based on the spec, Setting up static BIAS for GPU to improve the > rps performace. > > v2: rename reg defn to match spec. (Ville) > > v3: Updated bias setting for chv (Deepak) > > Signed-off-by: Deepak S <deepak.s@linux.intel.com> Matches the spec. Whether the chosen bias is really the best, I can't really say. But favoring the GPU does seem like a sensible idea if we want to keep the UI stuff fluid enough while there's some CPU heavy tasks running at the same time. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++ > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 36805b6..048987e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -670,6 +670,12 @@ enum skl_disp_power_wells { > #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 > #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 > > +#define VLV_TURBO_SOC_OVERRIDE 0x04 > +#define VLV_OVERRIDE_EN 1 > +#define VLV_SOC_TDP_EN (1 << 1) > +#define VLV_BIAS_CPU_125_SOC_875 (6 << 2) > +#define CHV_BIAS_CPU_50_SOC_50 (3 << 2) > + > #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 > > /* vlv2 north clock has */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 78c89ff..3689d0e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5065,6 +5065,12 @@ static void cherryview_enable_rps(struct drm_device *dev) > GEN6_RP_UP_BUSY_AVG | > GEN6_RP_DOWN_IDLE_AVG); > > + /* Setting Fixed Bias */ > + val = VLV_OVERRIDE_EN | > + VLV_SOC_TDP_EN | > + CHV_BIAS_CPU_50_SOC_50; > + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); > + > val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > > /* RPS code assumes GPLL is used */ > @@ -5149,6 +5155,12 @@ static void valleyview_enable_rps(struct drm_device *dev) > > I915_WRITE(GEN6_RC_CONTROL, rc6_mode); > > + /* Setting Fixed Bias */ > + val = VLV_OVERRIDE_EN | > + VLV_SOC_TDP_EN | > + VLV_BIAS_CPU_125_SOC_875; > + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); > + > val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > > /* RPS code assumes GPLL is used */ > -- > 1.9.1
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6283
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK -1 302/302 301/302
SNB 316/316 316/316
IVB -1 264/264 263/264
BYT -3 227/227 224/227
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*ILK igt@kms_flip@flip-vs-dpms-interruptible PASS(2) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:intel_pch_fifo_underrun_irq_handler[i915]]*ERROR*PCH_transcoder_A_FIFO_underrun@PCH transcoder A FIFO underrun
*IVB igt@gem_pwrite_pread@display-pwrite-blt-gtt_mmap-performance PASS(4) DMESG_FAIL(1)PASS(1)
(dmesg patch applied)drm:i915_context_is_banned[i915]]*ERROR*gpu_hanging_too_fast,banning@gpu hanging too
*BYT igt@gem_dummy_reloc_loop@render FAIL(1)PASS(7) TIMEOUT(1)PASS(1)
*BYT igt@gem_exec_parse@bitmasks FAIL(1)PASS(4) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found
WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x
BYT igt@gem_pipe_control_store_loop@fresh-buffer FAIL(1)TIMEOUT(4)PASS(4) TIMEOUT(1)PASS(1)
Note: You need to pay more attention to line start with '*'
On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote: > On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepak.s@linux.intel.com wrote: >> From: Deepak S <deepak.s@linux.intel.com> >> >> Based on the spec, Setting up static BIAS for GPU to improve the >> rps performace. >> >> v2: rename reg defn to match spec. (Ville) >> >> v3: Updated bias setting for chv (Deepak) >> >> Signed-off-by: Deepak S <deepak.s@linux.intel.com> > Matches the spec. Whether the chosen bias is really the best, I can't > really say. But favoring the GPU does seem like a sensible idea if we > want to keep the UI stuff fluid enough while there's some CPU heavy > tasks running at the same time. > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Thanks Ville for reviewing, Yes our aim is to keep user experience smooth. >> --- >> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ >> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++ >> 2 files changed, 18 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 36805b6..048987e 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -670,6 +670,12 @@ enum skl_disp_power_wells { >> #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 >> #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 >> >> +#define VLV_TURBO_SOC_OVERRIDE 0x04 >> +#define VLV_OVERRIDE_EN 1 >> +#define VLV_SOC_TDP_EN (1 << 1) >> +#define VLV_BIAS_CPU_125_SOC_875 (6 << 2) >> +#define CHV_BIAS_CPU_50_SOC_50 (3 << 2) >> + >> #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 >> >> /* vlv2 north clock has */ >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index 78c89ff..3689d0e 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -5065,6 +5065,12 @@ static void cherryview_enable_rps(struct drm_device *dev) >> GEN6_RP_UP_BUSY_AVG | >> GEN6_RP_DOWN_IDLE_AVG); >> >> + /* Setting Fixed Bias */ >> + val = VLV_OVERRIDE_EN | >> + VLV_SOC_TDP_EN | >> + CHV_BIAS_CPU_50_SOC_50; >> + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); >> + >> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); >> >> /* RPS code assumes GPLL is used */ >> @@ -5149,6 +5155,12 @@ static void valleyview_enable_rps(struct drm_device *dev) >> >> I915_WRITE(GEN6_RC_CONTROL, rc6_mode); >> >> + /* Setting Fixed Bias */ >> + val = VLV_OVERRIDE_EN | >> + VLV_SOC_TDP_EN | >> + VLV_BIAS_CPU_125_SOC_875; >> + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); >> + >> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); >> >> /* RPS code assumes GPLL is used */ >> -- >> 1.9.1
On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote: > > > On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote: > >On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepak.s@linux.intel.com wrote: > >>From: Deepak S <deepak.s@linux.intel.com> > >> > >>Based on the spec, Setting up static BIAS for GPU to improve the > >>rps performace. > >> > >>v2: rename reg defn to match spec. (Ville) > >> > >>v3: Updated bias setting for chv (Deepak) > >> > >>Signed-off-by: Deepak S <deepak.s@linux.intel.com> > >Matches the spec. Whether the chosen bias is really the best, I can't > >really say. But favoring the GPU does seem like a sensible idea if we > >want to keep the UI stuff fluid enough while there's some CPU heavy > >tasks running at the same time. > > > >Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Thanks Ville for reviewing, > Yes our aim is to keep user experience smooth. Since the aim is smooth UI ... how does this interact with the rps boosting that was just enabled with Chris' patches for vlv/chv too? A static bias seems a lot less what we want now that we should have something dynamic. Specifically I'm thinking of commit 6ad790c0f5ac55fd13f322c23519f0d6f0721864 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Tue Apr 7 16:20:31 2015 +0100 drm/i915: Boost GPU frequency if we detect outstanding pageflips Cheers, Daniel > > >>--- > >> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > >> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++ > >> 2 files changed, 18 insertions(+) > >> > >>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >>index 36805b6..048987e 100644 > >>--- a/drivers/gpu/drm/i915/i915_reg.h > >>+++ b/drivers/gpu/drm/i915/i915_reg.h > >>@@ -670,6 +670,12 @@ enum skl_disp_power_wells { > >> #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 > >> #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 > >>+#define VLV_TURBO_SOC_OVERRIDE 0x04 > >>+#define VLV_OVERRIDE_EN 1 > >>+#define VLV_SOC_TDP_EN (1 << 1) > >>+#define VLV_BIAS_CPU_125_SOC_875 (6 << 2) > >>+#define CHV_BIAS_CPU_50_SOC_50 (3 << 2) > >>+ > >> #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 > >> /* vlv2 north clock has */ > >>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > >>index 78c89ff..3689d0e 100644 > >>--- a/drivers/gpu/drm/i915/intel_pm.c > >>+++ b/drivers/gpu/drm/i915/intel_pm.c > >>@@ -5065,6 +5065,12 @@ static void cherryview_enable_rps(struct drm_device *dev) > >> GEN6_RP_UP_BUSY_AVG | > >> GEN6_RP_DOWN_IDLE_AVG); > >>+ /* Setting Fixed Bias */ > >>+ val = VLV_OVERRIDE_EN | > >>+ VLV_SOC_TDP_EN | > >>+ CHV_BIAS_CPU_50_SOC_50; > >>+ vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); > >>+ > >> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > >> /* RPS code assumes GPLL is used */ > >>@@ -5149,6 +5155,12 @@ static void valleyview_enable_rps(struct drm_device *dev) > >> I915_WRITE(GEN6_RC_CONTROL, rc6_mode); > >>+ /* Setting Fixed Bias */ > >>+ val = VLV_OVERRIDE_EN | > >>+ VLV_SOC_TDP_EN | > >>+ VLV_BIAS_CPU_125_SOC_875; > >>+ vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); > >>+ > >> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > >> /* RPS code assumes GPLL is used */ > >>-- > >>1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote: > On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote: > > > > > > On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote: > > >On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepak.s@linux.intel.com wrote: > > >>From: Deepak S <deepak.s@linux.intel.com> > > >> > > >>Based on the spec, Setting up static BIAS for GPU to improve the > > >>rps performace. > > >> > > >>v2: rename reg defn to match spec. (Ville) > > >> > > >>v3: Updated bias setting for chv (Deepak) > > >> > > >>Signed-off-by: Deepak S <deepak.s@linux.intel.com> > > >Matches the spec. Whether the chosen bias is really the best, I can't > > >really say. But favoring the GPU does seem like a sensible idea if we > > >want to keep the UI stuff fluid enough while there's some CPU heavy > > >tasks running at the same time. > > > > > >Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Thanks Ville for reviewing, > > Yes our aim is to keep user experience smooth. > > Since the aim is smooth UI ... how does this interact with the rps > boosting that was just enabled with Chris' patches for vlv/chv too? > > A static bias seems a lot less what we want now that we should have > something dynamic. Specifically I'm thinking of > > commit 6ad790c0f5ac55fd13f322c23519f0d6f0721864 > Author: Chris Wilson <chris@chris-wilson.co.uk> > Date: Tue Apr 7 16:20:31 2015 +0100 > > drm/i915: Boost GPU frequency if we detect outstanding pageflips Totally separate topic. This only affects how the Punit splits up the available energy credits between the CPU and the GPU. So only relevant when thermally constrained and both CPU and GPU would like to run faster than the limit allows. > > Cheers, Daniel > > > > > >>--- > > >> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > > >> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++ > > >> 2 files changed, 18 insertions(+) > > >> > > >>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > >>index 36805b6..048987e 100644 > > >>--- a/drivers/gpu/drm/i915/i915_reg.h > > >>+++ b/drivers/gpu/drm/i915/i915_reg.h > > >>@@ -670,6 +670,12 @@ enum skl_disp_power_wells { > > >> #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 > > >> #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 > > >>+#define VLV_TURBO_SOC_OVERRIDE 0x04 > > >>+#define VLV_OVERRIDE_EN 1 > > >>+#define VLV_SOC_TDP_EN (1 << 1) > > >>+#define VLV_BIAS_CPU_125_SOC_875 (6 << 2) > > >>+#define CHV_BIAS_CPU_50_SOC_50 (3 << 2) > > >>+ > > >> #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 > > >> /* vlv2 north clock has */ > > >>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > >>index 78c89ff..3689d0e 100644 > > >>--- a/drivers/gpu/drm/i915/intel_pm.c > > >>+++ b/drivers/gpu/drm/i915/intel_pm.c > > >>@@ -5065,6 +5065,12 @@ static void cherryview_enable_rps(struct drm_device *dev) > > >> GEN6_RP_UP_BUSY_AVG | > > >> GEN6_RP_DOWN_IDLE_AVG); > > >>+ /* Setting Fixed Bias */ > > >>+ val = VLV_OVERRIDE_EN | > > >>+ VLV_SOC_TDP_EN | > > >>+ CHV_BIAS_CPU_50_SOC_50; > > >>+ vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); > > >>+ > > >> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > > >> /* RPS code assumes GPLL is used */ > > >>@@ -5149,6 +5155,12 @@ static void valleyview_enable_rps(struct drm_device *dev) > > >> I915_WRITE(GEN6_RC_CONTROL, rc6_mode); > > >>+ /* Setting Fixed Bias */ > > >>+ val = VLV_OVERRIDE_EN | > > >>+ VLV_SOC_TDP_EN | > > >>+ VLV_BIAS_CPU_125_SOC_875; > > >>+ vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); > > >>+ > > >> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > > >> /* RPS code assumes GPLL is used */ > > >>-- > > >>1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch
On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote: > On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote: >> On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote: >>> >>> On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote: >>>> On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepak.s@linux.intel.com wrote: >>>>> From: Deepak S <deepak.s@linux.intel.com> >>>>> >>>>> Based on the spec, Setting up static BIAS for GPU to improve the >>>>> rps performace. >>>>> >>>>> v2: rename reg defn to match spec. (Ville) >>>>> >>>>> v3: Updated bias setting for chv (Deepak) >>>>> >>>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com> >>>> Matches the spec. Whether the chosen bias is really the best, I can't >>>> really say. But favoring the GPU does seem like a sensible idea if we >>>> want to keep the UI stuff fluid enough while there's some CPU heavy >>>> tasks running at the same time. >>>> >>>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >>> Thanks Ville for reviewing, >>> Yes our aim is to keep user experience smooth. >> Since the aim is smooth UI ... how does this interact with the rps >> boosting that was just enabled with Chris' patches for vlv/chv too? >> >> A static bias seems a lot less what we want now that we should have >> something dynamic. Specifically I'm thinking of >> >> commit 6ad790c0f5ac55fd13f322c23519f0d6f0721864 >> Author: Chris Wilson <chris@chris-wilson.co.uk> >> Date: Tue Apr 7 16:20:31 2015 +0100 >> >> drm/i915: Boost GPU frequency if we detect outstanding pageflips > Totally separate topic. This only affects how the Punit splits up the > available energy credits between the CPU and the GPU. So only relevant > when thermally constrained and both CPU and GPU would like to run > faster than the limit allows. > Thanks Ville. This is completely a different topic, more to do with punit budget constraints & this does not impact "Boot RPS logic" Thanks Deepak >> Cheers, Daniel >> >>>>> --- >>>>> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ >>>>> drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++++++ >>>>> 2 files changed, 18 insertions(+) >>>>> >>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >>>>> index 36805b6..048987e 100644 >>>>> --- a/drivers/gpu/drm/i915/i915_reg.h >>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h >>>>> @@ -670,6 +670,12 @@ enum skl_disp_power_wells { >>>>> #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 >>>>> #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 >>>>> +#define VLV_TURBO_SOC_OVERRIDE 0x04 >>>>> +#define VLV_OVERRIDE_EN 1 >>>>> +#define VLV_SOC_TDP_EN (1 << 1) >>>>> +#define VLV_BIAS_CPU_125_SOC_875 (6 << 2) >>>>> +#define CHV_BIAS_CPU_50_SOC_50 (3 << 2) >>>>> + >>>>> #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 >>>>> /* vlv2 north clock has */ >>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >>>>> index 78c89ff..3689d0e 100644 >>>>> --- a/drivers/gpu/drm/i915/intel_pm.c >>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c >>>>> @@ -5065,6 +5065,12 @@ static void cherryview_enable_rps(struct drm_device *dev) >>>>> GEN6_RP_UP_BUSY_AVG | >>>>> GEN6_RP_DOWN_IDLE_AVG); >>>>> + /* Setting Fixed Bias */ >>>>> + val = VLV_OVERRIDE_EN | >>>>> + VLV_SOC_TDP_EN | >>>>> + CHV_BIAS_CPU_50_SOC_50; >>>>> + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); >>>>> + >>>>> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); >>>>> /* RPS code assumes GPLL is used */ >>>>> @@ -5149,6 +5155,12 @@ static void valleyview_enable_rps(struct drm_device *dev) >>>>> I915_WRITE(GEN6_RC_CONTROL, rc6_mode); >>>>> + /* Setting Fixed Bias */ >>>>> + val = VLV_OVERRIDE_EN | >>>>> + VLV_SOC_TDP_EN | >>>>> + VLV_BIAS_CPU_125_SOC_875; >>>>> + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); >>>>> + >>>>> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); >>>>> /* RPS code assumes GPLL is used */ >>>>> -- >>>>> 1.9.1 >>> _______________________________________________ >>> Intel-gfx mailing list >>> Intel-gfx@lists.freedesktop.org >>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx >> -- >> Daniel Vetter >> Software Engineer, Intel Corporation >> http://blog.ffwll.ch
On Tue, May 05, 2015 at 01:12:41PM +0530, Deepak S wrote: > > > On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote: > >On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote: > >>On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote: > >>> > >>>On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote: > >>>>On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepak.s@linux.intel.com wrote: > >>>>>From: Deepak S <deepak.s@linux.intel.com> > >>>>> > >>>>>Based on the spec, Setting up static BIAS for GPU to improve the > >>>>>rps performace. > >>>>> > >>>>>v2: rename reg defn to match spec. (Ville) > >>>>> > >>>>>v3: Updated bias setting for chv (Deepak) > >>>>> > >>>>>Signed-off-by: Deepak S <deepak.s@linux.intel.com> > >>>>Matches the spec. Whether the chosen bias is really the best, I can't > >>>>really say. But favoring the GPU does seem like a sensible idea if we > >>>>want to keep the UI stuff fluid enough while there's some CPU heavy > >>>>tasks running at the same time. > >>>> > >>>>Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > >>>Thanks Ville for reviewing, > >>>Yes our aim is to keep user experience smooth. > >>Since the aim is smooth UI ... how does this interact with the rps > >>boosting that was just enabled with Chris' patches for vlv/chv too? > >> > >>A static bias seems a lot less what we want now that we should have > >>something dynamic. Specifically I'm thinking of > >> > >>commit 6ad790c0f5ac55fd13f322c23519f0d6f0721864 > >>Author: Chris Wilson <chris@chris-wilson.co.uk> > >>Date: Tue Apr 7 16:20:31 2015 +0100 > >> > >> drm/i915: Boost GPU frequency if we detect outstanding pageflips > >Totally separate topic. This only affects how the Punit splits up the > >available energy credits between the CPU and the GPU. So only relevant > >when thermally constrained and both CPU and GPU would like to run > >faster than the limit allows. > > > Thanks Ville. > > This is completely a different topic, more to do with punit budget > constraints & this does not impact "Boot RPS logic" Well I thought it'd be related since the justification was better UI interactivity. And that tends to not be a thermal constrained load but something really spike-y. And a static bias doesn't seem like a solution to that problem. I'll just go ahead and merge, but still feels like at least I don't know why exactly we need this. -Daniel
On Wednesday 06 May 2015 02:32 PM, Daniel Vetter wrote: > On Tue, May 05, 2015 at 01:12:41PM +0530, Deepak S wrote: >> >> On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote: >>> On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote: >>>> On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote: >>>>> On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä wrote: >>>>>> On Wed, Apr 29, 2015 at 08:36:24AM +0530, deepak.s@linux.intel.com wrote: >>>>>>> From: Deepak S <deepak.s@linux.intel.com> >>>>>>> >>>>>>> Based on the spec, Setting up static BIAS for GPU to improve the >>>>>>> rps performace. >>>>>>> >>>>>>> v2: rename reg defn to match spec. (Ville) >>>>>>> >>>>>>> v3: Updated bias setting for chv (Deepak) >>>>>>> >>>>>>> Signed-off-by: Deepak S <deepak.s@linux.intel.com> >>>>>> Matches the spec. Whether the chosen bias is really the best, I can't >>>>>> really say. But favoring the GPU does seem like a sensible idea if we >>>>>> want to keep the UI stuff fluid enough while there's some CPU heavy >>>>>> tasks running at the same time. >>>>>> >>>>>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >>>>> Thanks Ville for reviewing, >>>>> Yes our aim is to keep user experience smooth. >>>> Since the aim is smooth UI ... how does this interact with the rps >>>> boosting that was just enabled with Chris' patches for vlv/chv too? >>>> >>>> A static bias seems a lot less what we want now that we should have >>>> something dynamic. Specifically I'm thinking of >>>> >>>> commit 6ad790c0f5ac55fd13f322c23519f0d6f0721864 >>>> Author: Chris Wilson <chris@chris-wilson.co.uk> >>>> Date: Tue Apr 7 16:20:31 2015 +0100 >>>> >>>> drm/i915: Boost GPU frequency if we detect outstanding pageflips >>> Totally separate topic. This only affects how the Punit splits up the >>> available energy credits between the CPU and the GPU. So only relevant >>> when thermally constrained and both CPU and GPU would like to run >>> faster than the limit allows. >>> >> Thanks Ville. >> >> This is completely a different topic, more to do with punit budget >> constraints & this does not impact "Boot RPS logic" > Well I thought it'd be related since the justification was better UI > interactivity. And that tends to not be a thermal constrained load but > something really spike-y. And a static bias doesn't seem like a solution > to that problem. > > I'll just go ahead and merge, but still feels like at least I don't know > why exactly we need this. > -Daniel Hi Daniel, Dynamic power bias is not supported by the HW or FW :(. This static bias was recommended by HW team after analyzing the results on IA & GT Thanks Deepak
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 36805b6..048987e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -670,6 +670,12 @@ enum skl_disp_power_wells { #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 +#define VLV_TURBO_SOC_OVERRIDE 0x04 +#define VLV_OVERRIDE_EN 1 +#define VLV_SOC_TDP_EN (1 << 1) +#define VLV_BIAS_CPU_125_SOC_875 (6 << 2) +#define CHV_BIAS_CPU_50_SOC_50 (3 << 2) + #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 /* vlv2 north clock has */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 78c89ff..3689d0e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5065,6 +5065,12 @@ static void cherryview_enable_rps(struct drm_device *dev) GEN6_RP_UP_BUSY_AVG | GEN6_RP_DOWN_IDLE_AVG); + /* Setting Fixed Bias */ + val = VLV_OVERRIDE_EN | + VLV_SOC_TDP_EN | + CHV_BIAS_CPU_50_SOC_50; + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); /* RPS code assumes GPLL is used */ @@ -5149,6 +5155,12 @@ static void valleyview_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_CONTROL, rc6_mode); + /* Setting Fixed Bias */ + val = VLV_OVERRIDE_EN | + VLV_SOC_TDP_EN | + VLV_BIAS_CPU_125_SOC_875; + vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); + val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); /* RPS code assumes GPLL is used */