From patchwork Thu Apr 30 07:37:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vandana.kannan@intel.com X-Patchwork-Id: 6300111 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D282CBEEE1 for ; Thu, 30 Apr 2015 07:14:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 13ADD2012B for ; Thu, 30 Apr 2015 07:14:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4EC86201C0 for ; Thu, 30 Apr 2015 07:14:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF2E56E7C4; Thu, 30 Apr 2015 00:14:49 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F2476E7C7 for ; Thu, 30 Apr 2015 00:14:48 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 30 Apr 2015 00:14:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,675,1422950400"; d="scan'208";a="687874066" Received: from vkannan-desktop.iind.intel.com ([10.223.25.137]) by orsmga001.jf.intel.com with ESMTP; 30 Apr 2015 00:14:47 -0700 From: Vandana Kannan To: intel-gfx@lists.freedesktop.org Date: Thu, 30 Apr 2015 13:07:35 +0530 Message-Id: <1430379455-21244-3-git-send-email-vandana.kannan@intel.com> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1430379455-21244-1-git-send-email-vandana.kannan@intel.com> References: <1430379455-21244-1-git-send-email-vandana.kannan@intel.com> Subject: [Intel-gfx] [PATCH 3/3] drm/i915: eDP Panel Power sequencing add PPS reg set X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Second set of PPS registers have been defined but will be used when VBT provides a selection between the 2 sets of registers. Signed-off-by: Vandana Kannan Signed-off-by: A.Sunil Kamath Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 580f5cb..199a1747 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6345,6 +6345,12 @@ enum skl_disp_power_wells { #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 +/* BXT PPS changes - 2nd set of PPS registers */ +#define BXT_PP_STATUS2 0xc7300 +#define BXT_PP_CONTROL2 0xc7304 +#define BXT_PP_ON_DELAYS2 0xc7308 +#define BXT_PP_OFF_DELAYS2 0xc730c + #define PCH_DP_B 0xe4100 #define PCH_DPB_AUX_CH_CTL 0xe4110 #define PCH_DPB_AUX_CH_DATA1 0xe4114