| Message ID | 1430980259-5471-2-git-send-email-vandana.kannan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On to, 2015-05-07 at 12:00 +0530, Vandana Kannan wrote: > Making lane stagger calculation common for HDMI and DP > > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 49b9fd8..144d544 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1386,16 +1386,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > clk_div.m2_frac_en = clk_div.m2_frac != 0; > > vco = best_clock.vco; > - if (clock > 270000) > - clk_div.lanestagger = 0x18; > - else if (clock > 135000) > - clk_div.lanestagger = 0x0d; > - else if (clock > 67000) > - clk_div.lanestagger = 0x07; > - else if (clock > 33000) > - clk_div.lanestagger = 0x04; > - else > - clk_div.lanestagger = 0x02; > } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || > intel_encoder->type == INTEL_OUTPUT_EDP) { > struct drm_encoder *encoder = &intel_encoder->base; > @@ -1443,6 +1433,17 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > return false; > } > > + if (clock > 270000) > + clk_div.lanestagger = 0x18; > + else if (clock > 135000) > + clk_div.lanestagger = 0x0d; > + else if (clock > 67000) > + clk_div.lanestagger = 0x07; > + else if (clock > 33000) > + clk_div.lanestagger = 0x04; > + else > + clk_div.lanestagger = 0x02; > + Here as in patch 1/2 we don't need to have fixed values for lanestagger any more, so you can remove it from bxt_clk_div and use a local var instead. > crtc_state->dpll_hw_state.ebb0 = > PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); > crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6340
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB 316/316 316/316
IVB 342/342 342/342
BYT 286/286 286/286
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 49b9fd8..144d544 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1386,16 +1386,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, clk_div.m2_frac_en = clk_div.m2_frac != 0; vco = best_clock.vco; - if (clock > 270000) - clk_div.lanestagger = 0x18; - else if (clock > 135000) - clk_div.lanestagger = 0x0d; - else if (clock > 67000) - clk_div.lanestagger = 0x07; - else if (clock > 33000) - clk_div.lanestagger = 0x04; - else - clk_div.lanestagger = 0x02; } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || intel_encoder->type == INTEL_OUTPUT_EDP) { struct drm_encoder *encoder = &intel_encoder->base; @@ -1443,6 +1433,17 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, return false; } + if (clock > 270000) + clk_div.lanestagger = 0x18; + else if (clock > 135000) + clk_div.lanestagger = 0x0d; + else if (clock > 67000) + clk_div.lanestagger = 0x07; + else if (clock > 33000) + clk_div.lanestagger = 0x04; + else + clk_div.lanestagger = 0x02; + crtc_state->dpll_hw_state.ebb0 = PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
Making lane stagger calculation common for HDMI and DP Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-)