From patchwork Thu May 7 14:15:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Bragg X-Patchwork-Id: 6358591 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9D078BEEE1 for ; Thu, 7 May 2015 14:16:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 554AE2034E for ; Thu, 7 May 2015 14:16:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5C7FC20373 for ; Thu, 7 May 2015 14:16:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AAC2D6E84B; Thu, 7 May 2015 07:16:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 99D906E84D; Thu, 7 May 2015 07:16:11 -0700 (PDT) Received: by wiun10 with SMTP id n10so61662695wiu.1; Thu, 07 May 2015 07:16:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=jNnFgpaXEMVLI6zlD8+RV5H2nej3ukVk/mJPrQGobOM=; b=OH8whQuwc7tJ9lCZMRCXekac9eldj34G6UKTUahhh6deQOypgADhncLpXUyk6t4H7h KLjEJ4XgUKCe10+1Ptqhb5zan18eAcDUYDVtB22aNbSL/AuFENMB+ucRhul9+g61RCNJ /Q2B0aMqrkmdgoZ1ZO0mQ6VqrRFwAb82dcD/seuco8k4UmZLyYUutQRjlhpTzsgLmuAV JYdR+5Lv0Iy+a+dR7/UrCTkID0K5yqcYCRUFwXSr7lW6eEIVKyCN4+FxWcyewyYj5AAl m6iuxW9B1SyFNVjl6dVr2oOBPetcnMdaGahpYllIkA62IxGsasF1KbMwvsxCxWjTsJTD 5ndQ== X-Received: by 10.194.78.49 with SMTP id y17mr8060102wjw.131.1431008170906; Thu, 07 May 2015 07:16:10 -0700 (PDT) Received: from sixbynine.org (cpc26-heme10-2-0-cust305.9-1.cable.virginm.net. [86.3.57.50]) by mx.google.com with ESMTPSA id it5sm7662082wid.3.2015.05.07.07.16.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 May 2015 07:16:10 -0700 (PDT) From: Robert Bragg To: intel-gfx@lists.freedesktop.org Date: Thu, 7 May 2015 15:15:54 +0100 Message-Id: <1431008154-6833-12-git-send-email-robert@sixbynine.org> X-Mailer: git-send-email 2.3.2 In-Reply-To: <1431008154-6833-1-git-send-email-robert@sixbynine.org> References: <1431008154-6833-1-git-send-email-robert@sixbynine.org> Cc: Peter Zijlstra , David Airlie , linux-api@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ingo Molnar , Paul Mackerras , Arnaldo Carvalho de Melo , Daniel Vetter Subject: [Intel-gfx] [RFC PATCH 11/11] WIP: drm/i915: constrain unit gating while using OA X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We are still investigating the detailed requirements here, but there are some constraints we need to apply on unit level clock gating for reliable metrics (in particular for a reliable sampling period). Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_oa_perf.c | 70 +++++++++++++++++++++++++++++++------ drivers/gpu/drm/i915/i915_reg.h | 3 ++ 2 files changed, 63 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_oa_perf.c b/drivers/gpu/drm/i915/i915_oa_perf.c index d0dad5d..2a4121b 100644 --- a/drivers/gpu/drm/i915/i915_oa_perf.c +++ b/drivers/gpu/drm/i915/i915_oa_perf.c @@ -257,20 +257,46 @@ oa_buffer_destroy(struct drm_i915_private *i915) static void i915_oa_event_destroy(struct perf_event *event) { - struct drm_i915_private *i915 = - container_of(event->pmu, typeof(*i915), oa_pmu.pmu); + struct drm_i915_private *dev_priv = + container_of(event->pmu, typeof(*dev_priv), oa_pmu.pmu); WARN_ON(event->parent); - oa_buffer_destroy(i915); + I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) & + ~GEN6_RCZUNIT_CLOCK_GATE_DISABLE)); + //I915_WRITE(GEN6_UCGCTL3, (I915_READ(GEN6_UCGCTL3) & + // ~GEN6_OACSUNIT_CLOCK_GATE_DISABLE)); + I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) | + GEN7_DOP_CLOCK_GATE_ENABLE)); + + I915_WRITE(GEN7_ROW_CHICKEN2, + _MASKED_BIT_DISABLE(DOP_CLOCK_GATING_DISABLE)); + + //if (IS_HSW_GT2(dev_priv->dev)) { + if (1) { + I915_WRITE(HSW_ROW_CHICKEN2_GT2, + _MASKED_BIT_DISABLE(DOP_CLOCK_GATING_DISABLE)); + } + + if (IS_HSW_GT3(dev_priv->dev)) { + I915_WRITE(HSW_ROW_CHICKEN2_GT3_0, + _MASKED_BIT_DISABLE(DOP_CLOCK_GATING_DISABLE)); + I915_WRITE(HSW_ROW_CHICKEN2_GT3_1, + _MASKED_BIT_DISABLE(DOP_CLOCK_GATING_DISABLE)); + } - i915->oa_pmu.specific_ctx = NULL; + I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) & + ~GT_NOA_ENABLE)); + + oa_buffer_destroy(dev_priv); + + dev_priv->oa_pmu.specific_ctx = NULL; - BUG_ON(i915->oa_pmu.exclusive_event != event); - i915->oa_pmu.exclusive_event = NULL; + BUG_ON(dev_priv->oa_pmu.exclusive_event != event); + dev_priv->oa_pmu.exclusive_event = NULL; - intel_uncore_forcewake_put(i915, FORCEWAKE_ALL); - intel_runtime_pm_put(i915); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + intel_runtime_pm_put(dev_priv); } static void *vmap_oa_buffer(struct drm_i915_gem_object *obj) @@ -581,6 +607,32 @@ static int i915_oa_event_init(struct perf_event *event) BUG_ON(dev_priv->oa_pmu.exclusive_event); dev_priv->oa_pmu.exclusive_event = event; + + I915_WRITE(GDT_CHICKEN_BITS, GT_NOA_ENABLE); + + I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) | + GEN6_RCZUNIT_CLOCK_GATE_DISABLE)); + //I915_WRITE(GEN6_UCGCTL3, (I915_READ(GEN6_UCGCTL3) | + // GEN6_OACSUNIT_CLOCK_GATE_DISABLE)); + I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & + ~GEN7_DOP_CLOCK_GATE_ENABLE)); + + I915_WRITE(GEN7_ROW_CHICKEN2, + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + + //if (IS_HSW_GT2(dev_priv->dev)) { + if (1) { + I915_WRITE(HSW_ROW_CHICKEN2_GT2, + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + } + + if (IS_HSW_GT3(dev_priv->dev)) { + I915_WRITE(HSW_ROW_CHICKEN2_GT3_0, + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + I915_WRITE(HSW_ROW_CHICKEN2_GT3_1, + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); + } + event->destroy = i915_oa_event_destroy; /* PRM - observability performance counters: @@ -678,8 +730,6 @@ static void i915_oa_event_start(struct perf_event *event, int flags) WARN_ONCE(I915_READ(GEN6_UCGCTL3) & GEN6_OACSUNIT_CLOCK_GATE_DISABLE, "disabled OA unit level clock gating will result in incorrect per-context OA counters"); - I915_WRITE(GDT_CHICKEN_BITS, GT_NOA_ENABLE); - if (dev_priv->oa_pmu.metrics_set == I915_OA_METRICS_SET_3D) { config_oa_regs(dev_priv, hsw_profile_3d_mux_config, ARRAY_SIZE(hsw_profile_3d_mux_config)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d94932a..518b34c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7036,6 +7036,9 @@ enum skl_disp_power_wells { #define GEN7_ROW_CHICKEN2 0xe4f4 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4 +#define HSW_ROW_CHICKEN2_GT2 0xe5f4 +#define HSW_ROW_CHICKEN2_GT3_0 0xe6f4 +#define HSW_ROW_CHICKEN2_GT3_1 0xe7f4 #define DOP_CLOCK_GATING_DISABLE (1<<0) #define HSW_ROW_CHICKEN3 0xe49c