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[i-g-t,5/5] skl_compute_wrpll: Prefer even dividers

Message ID 1431019605-9786-6-git-send-email-damien.lespiau@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lespiau, Damien May 7, 2015, 5:26 p.m. UTC 
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 tools/skl_compute_wrpll.c | 7 +++++++
 1 file changed, 7 insertions(+)
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Patch

diff --git a/tools/skl_compute_wrpll.c b/tools/skl_compute_wrpll.c
index a3a6e58..55f2df4 100644
--- a/tools/skl_compute_wrpll.c
+++ b/tools/skl_compute_wrpll.c
@@ -431,6 +431,13 @@  skl_ddi_calculate_wrpll2(int clock /* in Hz */,
 						      dco_freq,
 						      p);
 			}
+
+			/*
+			 * If a solution is found with an even divider, prefer
+			 * this one.
+			 */
+			if (d == 0 && ctx.p)
+				break;
 		}
 	}