diff mbox

drm/i915: perform scaler_id check for skl+

Message ID 1431047764-29950-1-git-send-email-chandra.konduru@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chandra Konduru May 8, 2015, 1:16 a.m. UTC
Scaler id is added for skylake to handle its shared scalers.
This is not applicable for platforms before SKL. This patch limits
the scaler_id check during intel_pipe_config_compare to platforms
SKL and above.

Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Daniel Vetter May 8, 2015, 7:09 a.m. UTC | #1
On Thu, May 07, 2015 at 06:16:04PM -0700, Chandra Konduru wrote:
> Scaler id is added for skylake to handle its shared scalers.
> This is not applicable for platforms before SKL. This patch limits
> the scaler_id check during intel_pipe_config_compare to platforms
> SKL and above.

Please add a References: line here with the bug report from mailing lists.
Also please do a quick query of bugzilla, QA should have hit this too and
filed it.

Also please reference the commit that introduce this warning (or the most
likely one).

> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c297cdc..fc1b7f9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11846,7 +11846,9 @@ intel_pipe_config_compare(struct drm_device *dev,
>  		PIPE_CONF_CHECK_I(pch_pfit.size);
>  	}
>  
> -	PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> +	if (INTEL_INFO(dev)->gen >= 9) {
> +		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> +	}

In general all the state should be left as 0 on platforms that don't
support it. We only have conditionals for platforms where we compute
state, but for some hw-specific reason can't always reconstruct it from hw
state alone. Hence the correct fix would be to make sure that we leave
scaler_id == 0 in both compute_config and read_hw_state functions for gen
< 9.
-Daniel
Shuang He May 8, 2015, 5:10 p.m. UTC | #2
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6353
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  316/316              316/316
IVB                                  342/342              342/342
BYT                                  286/286              286/286
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
Chandra Konduru May 11, 2015, 9:29 p.m. UTC | #3
> > Scaler id is added for skylake to handle its shared scalers.
> > This is not applicable for platforms before SKL. This patch limits
> > the scaler_id check during intel_pipe_config_compare to platforms
> > SKL and above.
> 
> Please add a References: line here with the bug report from mailing lists.
> Also please do a quick query of bugzilla, QA should have hit this too and
> filed it.
> 
> Also please reference the commit that introduce this warning (or the most
> likely one).

Will update and send updated patch with references to commit and mailing list.

> >
> > -	PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> > +	if (INTEL_INFO(dev)->gen >= 9) {
> > +		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
> > +	}
> 
> In general all the state should be left as 0 on platforms that don't
> support it. We only have conditionals for platforms where we compute
> state, but for some hw-specific reason can't always reconstruct it from hw
> state alone. Hence the correct fix would be to make sure that we leave
> scaler_id == 0 in both compute_config and read_hw_state functions for gen
> < 9.	

Working on updated patch leaving scaler_id as 0 for gen<9 and sending soon.
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c297cdc..fc1b7f9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11846,7 +11846,9 @@  intel_pipe_config_compare(struct drm_device *dev,
 		PIPE_CONF_CHECK_I(pch_pfit.size);
 	}
 
-	PIPE_CONF_CHECK_I(scaler_state.scaler_id);
+	if (INTEL_INFO(dev)->gen >= 9) {
+		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
+	}
 
 	/* BDW+ don't expose a synchronous way to read the state */
 	if (IS_HASWELL(dev))