From patchwork Thu May 21 17:40:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Bragg X-Patchwork-Id: 6457861 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 586BF9F399 for ; Thu, 21 May 2015 17:40:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 06CA02051D for ; Thu, 21 May 2015 17:40:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1FD1820524 for ; Thu, 21 May 2015 17:40:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7CBA46E98F; Thu, 21 May 2015 10:40:32 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wg0-f48.google.com (mail-wg0-f48.google.com [74.125.82.48]) by gabe.freedesktop.org (Postfix) with ESMTP id CD87D6E98F; Thu, 21 May 2015 10:40:30 -0700 (PDT) Received: by wghq2 with SMTP id q2so93020329wgh.1; Thu, 21 May 2015 10:40:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZW6pWtm7izovAqa7lKkMXuOOe0HmtI1SXpmvCno70Cs=; b=M+nYDMqfw9GoBl0l8/QWiSJJnTPoAO27KDldiSxQi7JWTJnuOFIoe+mdHDplmNxJ0f 5UTHGlgswssXG0hjxzoS9ZqNeCfex7+TIvcxc4ivYzluCkEfjX57zq9blV5iS4sWkkWd fXUaQ+z2G9GMxnZ7fpckQ872AilnitCkvaPZLl7wEiPMSXT6dvi4r2rROD1RiOMInaiK LvQp5rgqh5ZgOSLYNbWn476T8Gr89SZcSlY/LCOwktzC4exumTztYOMk2D1+x2Sb4hpY 7MirjMJDo3q+HoC0r8bl65hOngSsUMQtXOqpR4jUdM3kbBM/+QTu5yHDqR9qaIy0s19/ 5xMA== X-Received: by 10.194.24.196 with SMTP id w4mr7286482wjf.137.1432230029963; Thu, 21 May 2015 10:40:29 -0700 (PDT) Received: from sixbynine.org ([83.217.123.106]) by mx.google.com with ESMTPSA id ny7sm3890841wic.11.2015.05.21.10.40.29 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 May 2015 10:40:29 -0700 (PDT) From: Robert Bragg To: intel-gfx@lists.freedesktop.org Date: Thu, 21 May 2015 18:40:28 +0100 Message-Id: <1432230028-30987-1-git-send-email-robert@sixbynine.org> X-Mailer: git-send-email 2.4.1 In-Reply-To: <20150520121226.GA11195@gmail.com> References: <20150520121226.GA11195@gmail.com> Cc: Peter Zijlstra , David Airlie , linux-api@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ingo Molnar , Paul Mackerras , Arnaldo Carvalho de Melo , Daniel Vetter Subject: [Intel-gfx] [RFC PATCH] perf: enable fsync to flush buffered samples X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of having a PERF_EVENT_IOC_FLUSH ioctl this instead allows userspace to use fsync for flushing pmu samples, as suggested by Ingo Molnar - thanks. For reference I've also pushed a patch to my Mesa branch to test this: https://github.com/rib/mesa wip/rib/oa-hsw-4.0.0 - Robert --- >8 --- To allow for pmus that may have internal buffering (e.g. the hardware writes out data to a circular buffer which is only periodically forwarded to userspace via perf) this enables userspace to explicitly ensure it has received all samples before a point in time. Signed-off-by: Robert Bragg --- include/linux/perf_event.h | 7 +++++++ kernel/events/core.c | 23 +++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 04e98c8..d7fac05 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -305,6 +305,13 @@ struct pmu { * Free pmu-private AUX data structures */ void (*free_aux) (void *aux); /* optional */ + + /* + * Flush buffered samples (E.g. for pmu hardware that writes samples to + * some intermediate buffer) userspace may need to explicitly ensure + * such samples have been forwarded to perf. + */ + int (*flush) (struct perf_event *event); /*optional */ }; /** diff --git a/kernel/events/core.c b/kernel/events/core.c index 2ba89a1..a604e0c 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -4728,6 +4728,28 @@ static int perf_fasync(int fd, struct file *filp, int on) return 0; } +static int perf_fsync(struct file *filp, loff_t start, loff_t end, int datasync) +{ + struct perf_event *event = filp->private_data; + struct perf_event_context *ctx; + int ret; + + /* We don't have a use for synchonizing a specific range, or datasync + * but lets not silently ignore them in case we think of uses later... + */ + if (start != 0 || end != LLONG_MAX || datasync != 0) + return -EINVAL; + + if (!event->pmu->flush) + return 0; + + ctx = perf_event_ctx_lock(event); + ret = event->pmu->flush(event); + perf_event_ctx_unlock(event, ctx); + + return ret; +} + static const struct file_operations perf_fops = { .llseek = no_llseek, .release = perf_release, @@ -4737,6 +4759,7 @@ static const struct file_operations perf_fops = { .compat_ioctl = perf_compat_ioctl, .mmap = perf_mmap, .fasync = perf_fasync, + .fsync = perf_fsync, }; /*