| Message ID | 1432282962-3530-7-git-send-email-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, May 22, 2015 at 11:22:36AM +0300, Mika Kahola wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Rather than reading out the current cdclk value use the cached value we > have tucked away in dev_priv. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > v2: Rebased to the latest > v3: Rebased to the latest > > Reviewed-by: Mika Kahola <mika.kahola@intel.com> > > Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 3 +-- > drivers/gpu/drm/i915/intel_dp.c | 5 +++-- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 75b11d6..fcd4112 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6406,8 +6406,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, > > /* FIXME should check pixel clock limits on all platforms */ > if (INTEL_INFO(dev)->gen < 4) { > - int clock_limit = > - dev_priv->display.get_display_clock_speed(dev); > + int clock_limit = dev_priv->cdclk_freq; > > /* > * Enable pixel doubling when the dot clock > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 0edc305..2dd4d28 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -708,7 +708,8 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > return 0; > > if (intel_dig_port->port == PORT_A) { > - return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000); > + return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); > + > } else { > return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); > } > @@ -723,7 +724,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) > if (intel_dig_port->port == PORT_A) { > if (index) > return 0; > - return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000); > + return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); > } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { > /* Workaround for non-ULT HSW */ > switch (index) { > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ce1d079..0046cb4 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1815,7 +1815,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) > linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, > mode->crtc_clock); > ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, > - dev_priv->display.get_display_clock_speed(dev_priv->dev)); > + dev_priv->cdclk_freq); > > return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | > PIPE_WM_LINETIME_TIME(linetime); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 75b11d6..fcd4112 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6406,8 +6406,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, /* FIXME should check pixel clock limits on all platforms */ if (INTEL_INFO(dev)->gen < 4) { - int clock_limit = - dev_priv->display.get_display_clock_speed(dev); + int clock_limit = dev_priv->cdclk_freq; /* * Enable pixel doubling when the dot clock diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 0edc305..2dd4d28 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -708,7 +708,8 @@ static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) return 0; if (intel_dig_port->port == PORT_A) { - return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000); + return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000); + } else { return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); } @@ -723,7 +724,7 @@ static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) if (intel_dig_port->port == PORT_A) { if (index) return 0; - return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000); + return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { /* Workaround for non-ULT HSW */ switch (index) { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ce1d079..0046cb4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1815,7 +1815,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, mode->crtc_clock); ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, - dev_priv->display.get_display_clock_speed(dev_priv->dev)); + dev_priv->cdclk_freq); return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | PIPE_WM_LINETIME_TIME(linetime);