| Message ID | 1432632098-12543-1-git-send-email-sonika.jindal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote: > BXT supports following intermediate link rates for edp: > 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz. > Adding support for programming the intermediate rates. > > v2: Adding clock in bxt_clk_div struct and then look for the entry with > required rate (Ville) > v3: 'clock' has the selected value, no need to use link_bw or rate_select > for selecting pll(Ville) > v4: Make bxt_dp_clk_val const and remove size (Ville) > v5: Rebased > > Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> This time applied for really. Somehow the previous attempt fell short, and digging into git reflog didn't reveal any clues. Sorry for the mess I've made. -Daniel > --- > drivers/gpu/drm/i915/intel_ddi.c | 40 +++++++++++++++----------------------- > drivers/gpu/drm/i915/intel_dp.c | 7 ++++++- > 2 files changed, 22 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index cacb07b..eb3238a 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc, > > /* bxt clock parameters */ > struct bxt_clk_div { > + int clock; > uint32_t p1; > uint32_t p2; > uint32_t m2_int; > @@ -1343,14 +1344,14 @@ struct bxt_clk_div { > }; > > /* pre-calculated values for DP linkrates */ > -static struct bxt_clk_div bxt_dp_clk_val[7] = { > - /* 162 */ {4, 2, 32, 1677722, 1, 1}, > - /* 270 */ {4, 1, 27, 0, 0, 1}, > - /* 540 */ {2, 1, 27, 0, 0, 1}, > - /* 216 */ {3, 2, 32, 1677722, 1, 1}, > - /* 243 */ {4, 1, 24, 1258291, 1, 1}, > - /* 324 */ {4, 1, 32, 1677722, 1, 1}, > - /* 432 */ {3, 1, 32, 1677722, 1, 1} > +static const struct bxt_clk_div bxt_dp_clk_val[] = { > + {162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, > + {270000, 4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd}, > + {540000, 2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18}, > + {216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, > + {243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd}, > + {324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, > + {432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18} > }; > > static bool > @@ -1390,24 +1391,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > vco = best_clock.vco; > } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || > intel_encoder->type == INTEL_OUTPUT_EDP) { > - struct drm_encoder *encoder = &intel_encoder->base; > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + int i; > > - switch (intel_dp->link_bw) { > - case DP_LINK_BW_1_62: > - clk_div = bxt_dp_clk_val[0]; > - break; > - case DP_LINK_BW_2_7: > - clk_div = bxt_dp_clk_val[1]; > - break; > - case DP_LINK_BW_5_4: > - clk_div = bxt_dp_clk_val[2]; > - break; > - default: > - clk_div = bxt_dp_clk_val[0]; > - DRM_ERROR("Unknown link rate\n"); > + clk_div = bxt_dp_clk_val[0]; > + for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { > + if (bxt_dp_clk_val[i].clock == clock) { > + clk_div = bxt_dp_clk_val[i]; > + break; > + } > } > - vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; > } > > dco_amp = 15; > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index abd442a..bd0f958 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = { > { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } > }; > > +static const int bxt_rates[] = { 162000, 216000, 243000, 270000, > + 324000, 432000, 540000 }; > static const int skl_rates[] = { 162000, 216000, 270000, > 324000, 432000, 540000 }; > static const int chv_rates[] = { 162000, 202500, 210000, 216000, > @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) > static int > intel_dp_source_rates(struct drm_device *dev, const int **source_rates) > { > - if (IS_SKYLAKE(dev)) { > + if (IS_BROXTON(dev)) { > + *source_rates = bxt_rates; > + return ARRAY_SIZE(bxt_rates); > + } else if (IS_SKYLAKE(dev)) { > *source_rates = skl_rates; > return ARRAY_SIZE(skl_rates); > } else if (IS_CHERRYVIEW(dev)) { > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, 26 May 2015, Sonika Jindal <sonika.jindal@intel.com> wrote: > BXT supports following intermediate link rates for edp: > 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz. > Adding support for programming the intermediate rates. > > v2: Adding clock in bxt_clk_div struct and then look for the entry with > required rate (Ville) > v3: 'clock' has the selected value, no need to use link_bw or rate_select > for selecting pll(Ville) > v4: Make bxt_dp_clk_val const and remove size (Ville) > v5: Rebased > > Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 40 +++++++++++++++----------------------- > drivers/gpu/drm/i915/intel_dp.c | 7 ++++++- > 2 files changed, 22 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index cacb07b..eb3238a 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc, > > /* bxt clock parameters */ > struct bxt_clk_div { > + int clock; > uint32_t p1; > uint32_t p2; > uint32_t m2_int; > @@ -1343,14 +1344,14 @@ struct bxt_clk_div { > }; > > /* pre-calculated values for DP linkrates */ > -static struct bxt_clk_div bxt_dp_clk_val[7] = { > - /* 162 */ {4, 2, 32, 1677722, 1, 1}, > - /* 270 */ {4, 1, 27, 0, 0, 1}, > - /* 540 */ {2, 1, 27, 0, 0, 1}, > - /* 216 */ {3, 2, 32, 1677722, 1, 1}, > - /* 243 */ {4, 1, 24, 1258291, 1, 1}, > - /* 324 */ {4, 1, 32, 1677722, 1, 1}, > - /* 432 */ {3, 1, 32, 1677722, 1, 1} > +static const struct bxt_clk_div bxt_dp_clk_val[] = { > + {162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, > + {270000, 4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd}, > + {540000, 2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18}, > + {216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, > + {243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd}, > + {324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, > + {432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18} > }; > > static bool > @@ -1390,24 +1391,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, > vco = best_clock.vco; > } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || > intel_encoder->type == INTEL_OUTPUT_EDP) { > - struct drm_encoder *encoder = &intel_encoder->base; > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + int i; > > - switch (intel_dp->link_bw) { > - case DP_LINK_BW_1_62: > - clk_div = bxt_dp_clk_val[0]; > - break; > - case DP_LINK_BW_2_7: > - clk_div = bxt_dp_clk_val[1]; > - break; > - case DP_LINK_BW_5_4: > - clk_div = bxt_dp_clk_val[2]; > - break; > - default: > - clk_div = bxt_dp_clk_val[0]; > - DRM_ERROR("Unknown link rate\n"); > + clk_div = bxt_dp_clk_val[0]; > + for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { > + if (bxt_dp_clk_val[i].clock == clock) { > + clk_div = bxt_dp_clk_val[i]; > + break; > + } > } > - vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; Without vco set, won't this hit the DRM_ERROR("Invalid VCO\n"); path right below? BR, Jani. > } > > dco_amp = 15; > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index abd442a..bd0f958 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = { > { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } > }; > > +static const int bxt_rates[] = { 162000, 216000, 243000, 270000, > + 324000, 432000, 540000 }; > static const int skl_rates[] = { 162000, 216000, 270000, > 324000, 432000, 540000 }; > static const int chv_rates[] = { 162000, 202500, 210000, 216000, > @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) > static int > intel_dp_source_rates(struct drm_device *dev, const int **source_rates) > { > - if (IS_SKYLAKE(dev)) { > + if (IS_BROXTON(dev)) { > + *source_rates = bxt_rates; > + return ARRAY_SIZE(bxt_rates); > + } else if (IS_SKYLAKE(dev)) { > *source_rates = skl_rates; > return ARRAY_SIZE(skl_rates); > } else if (IS_CHERRYVIEW(dev)) { > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, 26 May 2015, Daniel Vetter <daniel@ffwll.ch> wrote: > On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote: >> BXT supports following intermediate link rates for edp: >> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz. >> Adding support for programming the intermediate rates. >> >> v2: Adding clock in bxt_clk_div struct and then look for the entry with >> required rate (Ville) >> v3: 'clock' has the selected value, no need to use link_bw or rate_select >> for selecting pll(Ville) >> v4: Make bxt_dp_clk_val const and remove size (Ville) >> v5: Rebased >> >> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> >> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > This time applied for really. Somehow the previous attempt fell short, and > digging into git reflog didn't reveal any clues. Sorry for the mess I've > made. Please drop this, the rebase does not take into account commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f Author: Vandana Kannan <vandana.kannan@intel.com> Date: Wed May 13 12:18:52 2015 +0530 drm/i915/bxt: Port PLL programming BUN and now leaves vco at zero. BR, Jani. > -Daniel > >> --- >> drivers/gpu/drm/i915/intel_ddi.c | 40 +++++++++++++++----------------------- >> drivers/gpu/drm/i915/intel_dp.c | 7 ++++++- >> 2 files changed, 22 insertions(+), 25 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> index cacb07b..eb3238a 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc, >> >> /* bxt clock parameters */ >> struct bxt_clk_div { >> + int clock; >> uint32_t p1; >> uint32_t p2; >> uint32_t m2_int; >> @@ -1343,14 +1344,14 @@ struct bxt_clk_div { >> }; >> >> /* pre-calculated values for DP linkrates */ >> -static struct bxt_clk_div bxt_dp_clk_val[7] = { >> - /* 162 */ {4, 2, 32, 1677722, 1, 1}, >> - /* 270 */ {4, 1, 27, 0, 0, 1}, >> - /* 540 */ {2, 1, 27, 0, 0, 1}, >> - /* 216 */ {3, 2, 32, 1677722, 1, 1}, >> - /* 243 */ {4, 1, 24, 1258291, 1, 1}, >> - /* 324 */ {4, 1, 32, 1677722, 1, 1}, >> - /* 432 */ {3, 1, 32, 1677722, 1, 1} >> +static const struct bxt_clk_div bxt_dp_clk_val[] = { >> + {162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, >> + {270000, 4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd}, >> + {540000, 2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18}, >> + {216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, >> + {243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd}, >> + {324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, >> + {432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18} >> }; >> >> static bool >> @@ -1390,24 +1391,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, >> vco = best_clock.vco; >> } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || >> intel_encoder->type == INTEL_OUTPUT_EDP) { >> - struct drm_encoder *encoder = &intel_encoder->base; >> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); >> + int i; >> >> - switch (intel_dp->link_bw) { >> - case DP_LINK_BW_1_62: >> - clk_div = bxt_dp_clk_val[0]; >> - break; >> - case DP_LINK_BW_2_7: >> - clk_div = bxt_dp_clk_val[1]; >> - break; >> - case DP_LINK_BW_5_4: >> - clk_div = bxt_dp_clk_val[2]; >> - break; >> - default: >> - clk_div = bxt_dp_clk_val[0]; >> - DRM_ERROR("Unknown link rate\n"); >> + clk_div = bxt_dp_clk_val[0]; >> + for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { >> + if (bxt_dp_clk_val[i].clock == clock) { >> + clk_div = bxt_dp_clk_val[i]; >> + break; >> + } >> } >> - vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; >> } >> >> dco_amp = 15; >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index abd442a..bd0f958 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = { >> { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } >> }; >> >> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000, >> + 324000, 432000, 540000 }; >> static const int skl_rates[] = { 162000, 216000, 270000, >> 324000, 432000, 540000 }; >> static const int chv_rates[] = { 162000, 202500, 210000, 216000, >> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) >> static int >> intel_dp_source_rates(struct drm_device *dev, const int **source_rates) >> { >> - if (IS_SKYLAKE(dev)) { >> + if (IS_BROXTON(dev)) { >> + *source_rates = bxt_rates; >> + return ARRAY_SIZE(bxt_rates); >> + } else if (IS_SKYLAKE(dev)) { >> *source_rates = skl_rates; >> return ARRAY_SIZE(skl_rates); >> } else if (IS_CHERRYVIEW(dev)) { >> -- >> 1.7.10.4 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, May 26, 2015 at 12:57:26PM +0300, Jani Nikula wrote: > On Tue, 26 May 2015, Daniel Vetter <daniel@ffwll.ch> wrote: > > On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote: > >> BXT supports following intermediate link rates for edp: > >> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz. > >> Adding support for programming the intermediate rates. > >> > >> v2: Adding clock in bxt_clk_div struct and then look for the entry with > >> required rate (Ville) > >> v3: 'clock' has the selected value, no need to use link_bw or rate_select > >> for selecting pll(Ville) > >> v4: Make bxt_dp_clk_val const and remove size (Ville) > >> v5: Rebased > >> > >> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> > >> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > This time applied for really. Somehow the previous attempt fell short, and > > digging into git reflog didn't reveal any clues. Sorry for the mess I've > > made. > > Please drop this, the rebase does not take into account > > commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f > Author: Vandana Kannan <vandana.kannan@intel.com> > Date: Wed May 13 12:18:52 2015 +0530 > > drm/i915/bxt: Port PLL programming BUN > > and now leaves vco at zero. Yeah dropped again. I didn't do the rebase myself because of these functional conflicts, but then totally forgot to check that Sonika bothered to run the patch first. Generally when I ask for a rebase it means that there's something nontrivial going on ... Thanks, Daniel
On 5/26/2015 3:29 PM, Daniel Vetter wrote: > On Tue, May 26, 2015 at 12:57:26PM +0300, Jani Nikula wrote: >> On Tue, 26 May 2015, Daniel Vetter <daniel@ffwll.ch> wrote: >>> On Tue, May 26, 2015 at 02:51:38PM +0530, Sonika Jindal wrote: >>>> BXT supports following intermediate link rates for edp: >>>> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz. >>>> Adding support for programming the intermediate rates. >>>> >>>> v2: Adding clock in bxt_clk_div struct and then look for the entry with >>>> required rate (Ville) >>>> v3: 'clock' has the selected value, no need to use link_bw or rate_select >>>> for selecting pll(Ville) >>>> v4: Make bxt_dp_clk_val const and remove size (Ville) >>>> v5: Rebased >>>> >>>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> >>>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> >>> >>> This time applied for really. Somehow the previous attempt fell short, and >>> digging into git reflog didn't reveal any clues. Sorry for the mess I've >>> made. >> >> Please drop this, the rebase does not take into account >> >> commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f >> Author: Vandana Kannan <vandana.kannan@intel.com> >> Date: Wed May 13 12:18:52 2015 +0530 >> >> drm/i915/bxt: Port PLL programming BUN >> >> and now leaves vco at zero. > > Yeah dropped again. I didn't do the rebase myself because of these > functional conflicts, but then totally forgot to check that Sonika > bothered to run the patch first. > > Generally when I ask for a rebase it means that there's something > nontrivial going on ... > :( Completely my mistake. Removed that line by mistake :( > Thanks, Daniel >
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index cacb07b..eb3238a 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc, /* bxt clock parameters */ struct bxt_clk_div { + int clock; uint32_t p1; uint32_t p2; uint32_t m2_int; @@ -1343,14 +1344,14 @@ struct bxt_clk_div { }; /* pre-calculated values for DP linkrates */ -static struct bxt_clk_div bxt_dp_clk_val[7] = { - /* 162 */ {4, 2, 32, 1677722, 1, 1}, - /* 270 */ {4, 1, 27, 0, 0, 1}, - /* 540 */ {2, 1, 27, 0, 0, 1}, - /* 216 */ {3, 2, 32, 1677722, 1, 1}, - /* 243 */ {4, 1, 24, 1258291, 1, 1}, - /* 324 */ {4, 1, 32, 1677722, 1, 1}, - /* 432 */ {3, 1, 32, 1677722, 1, 1} +static const struct bxt_clk_div bxt_dp_clk_val[] = { + {162000, 4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, + {270000, 4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd}, + {540000, 2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18}, + {216000, 3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, + {243000, 4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd}, + {324000, 4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, + {432000, 3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18} }; static bool @@ -1390,24 +1391,15 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, vco = best_clock.vco; } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || intel_encoder->type == INTEL_OUTPUT_EDP) { - struct drm_encoder *encoder = &intel_encoder->base; - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + int i; - switch (intel_dp->link_bw) { - case DP_LINK_BW_1_62: - clk_div = bxt_dp_clk_val[0]; - break; - case DP_LINK_BW_2_7: - clk_div = bxt_dp_clk_val[1]; - break; - case DP_LINK_BW_5_4: - clk_div = bxt_dp_clk_val[2]; - break; - default: - clk_div = bxt_dp_clk_val[0]; - DRM_ERROR("Unknown link rate\n"); + clk_div = bxt_dp_clk_val[0]; + for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { + if (bxt_dp_clk_val[i].clock == clock) { + clk_div = bxt_dp_clk_val[i]; + break; + } } - vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; } dco_amp = 15; diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index abd442a..bd0f958 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = { { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } }; +static const int bxt_rates[] = { 162000, 216000, 243000, 270000, + 324000, 432000, 540000 }; static const int skl_rates[] = { 162000, 216000, 270000, 324000, 432000, 540000 }; static const int chv_rates[] = { 162000, 202500, 210000, 216000, @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) static int intel_dp_source_rates(struct drm_device *dev, const int **source_rates) { - if (IS_SKYLAKE(dev)) { + if (IS_BROXTON(dev)) { + *source_rates = bxt_rates; + return ARRAY_SIZE(bxt_rates); + } else if (IS_SKYLAKE(dev)) { *source_rates = skl_rates; return ARRAY_SIZE(skl_rates); } else if (IS_CHERRYVIEW(dev)) {