drm/i915/bxt: edp1.4 Intermediate Freq support

Message ID	1432642813-6917-1-git-send-email-sonika.jindal@intel.com (mailing list archive)
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Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Sonika Jindal <sonika.jindal@intel.com> To: intel-gfx@lists.freedesktop.org Date: Tue, 26 May 2015 17:50:13 +0530 Message-Id: <1432642813-6917-1-git-send-email-sonika.jindal@intel.com> In-Reply-To: <5564493F.6030004@intel.com> References: <5564493F.6030004@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

Message ID

1432642813-6917-1-git-send-email-sonika.jindal@intel.com (mailing list archive)

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From: Sonika Jindal <sonika.jindal@intel.com>
To: intel-gfx@lists.freedesktop.org
Date: Tue, 26 May 2015 17:50:13 +0530
Message-Id: <1432642813-6917-1-git-send-email-sonika.jindal@intel.com>
In-Reply-To: <5564493F.6030004@intel.com>
References: <5564493F.6030004@intel.com>
MIME-Version: 1.0
Subject: [Intel-gfx] [PATCH] drm/i915/bxt: edp1.4 Intermediate Freq support
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Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

Commit Message

sonika.jindal@intel.com May 26, 2015, 12:20 p.m. UTC

BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.

v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_bw or rate_select
for selecting pll(Ville)
v4: Make bxt_dp_clk_val const and remove size (Ville)
v5: Rebased
v6: Removed setting of vco while rebasing in v5, adding it back

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>(v4)
---
 drivers/gpu/drm/i915/intel_ddi.c |   39 ++++++++++++++++----------------------
 drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
 2 files changed, 22 insertions(+), 24 deletions(-)

Comments

sonika.jindal@intel.com June 3, 2015, 5:19 a.m. UTC | #1

Hi Vandana,

Can you please review the v6 of this patch?

This was rebased recently on top of your patch:
  commit b6dc71f38a84e36c5445b95f9f7a2dac6b25636f
  Author: Vandana Kannan <vandana.kannan@intel.com>
  Date:   Wed May 13 12:18:52 2015 +0530

       drm/i915/bxt: Port PLL programming BUN

Thanks,
Sonika

On 5/26/2015 5:50 PM, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> for selecting pll(Ville)
> v4: Make bxt_dp_clk_val const and remove size (Ville)
> v5: Rebased
> v6: Removed setting of vco while rebasing in v5, adding it back
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>(v4)
> ---
>   drivers/gpu/drm/i915/intel_ddi.c |   39 ++++++++++++++++----------------------
>   drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>   2 files changed, 22 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..2a2518d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>
>   /* bxt clock parameters */
>   struct bxt_clk_div {
> +	int clock;
>   	uint32_t p1;
>   	uint32_t p2;
>   	uint32_t m2_int;
> @@ -1343,14 +1344,14 @@ struct bxt_clk_div {
>   };
>
>   /* pre-calculated values for DP linkrates */
> -static struct bxt_clk_div bxt_dp_clk_val[7] = {
> -	/* 162 */ {4, 2, 32, 1677722, 1, 1},
> -	/* 270 */ {4, 1, 27,       0, 0, 1},
> -	/* 540 */ {2, 1, 27,       0, 0, 1},
> -	/* 216 */ {3, 2, 32, 1677722, 1, 1},
> -	/* 243 */ {4, 1, 24, 1258291, 1, 1},
> -	/* 324 */ {4, 1, 32, 1677722, 1, 1},
> -	/* 432 */ {3, 1, 32, 1677722, 1, 1}
> +static const struct bxt_clk_div bxt_dp_clk_val[] = {
> +	{162000, 4, 2, 32, 1677722, 1, 1},
> +	{270000, 4, 1, 27,       0, 0, 1},
> +	{540000, 2, 1, 27,       0, 0, 1},
> +	{216000, 3, 2, 32, 1677722, 1, 1},
> +	{243000, 4, 1, 24, 1258291, 1, 1},
> +	{324000, 4, 1, 32, 1677722, 1, 1},
> +	{432000, 3, 1, 32, 1677722, 1, 1}
>   };
>
>   static bool
> @@ -1390,22 +1391,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		vco = best_clock.vco;
>   	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>   			intel_encoder->type == INTEL_OUTPUT_EDP) {
> -		struct drm_encoder *encoder = &intel_encoder->base;
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		int i;
>
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> -			clk_div = bxt_dp_clk_val[0];
> -			break;
> -		case DP_LINK_BW_2_7:
> -			clk_div = bxt_dp_clk_val[1];
> -			break;
> -		case DP_LINK_BW_5_4:
> -			clk_div = bxt_dp_clk_val[2];
> -			break;
> -		default:
> -			clk_div = bxt_dp_clk_val[0];
> -			DRM_ERROR("Unknown link rate\n");
> +		clk_div = bxt_dp_clk_val[0];
> +		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
> +			if (bxt_dp_clk_val[i].clock == clock) {
> +				clk_div = bxt_dp_clk_val[i];
> +				break;
> +			}
>   		}
>   		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>   	}
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index abd442a..bd0f958 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>   };
>
> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> +				  324000, 432000, 540000 };
>   static const int skl_rates[] = { 162000, 216000, 270000,
>   				  324000, 432000, 540000 };
>   static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>   static int
>   intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>   {
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		*source_rates = bxt_rates;
> +		return ARRAY_SIZE(bxt_rates);
> +	} else if (IS_SKYLAKE(dev)) {
>   		*source_rates = skl_rates;
>   		return ARRAY_SIZE(skl_rates);
>   	} else if (IS_CHERRYVIEW(dev)) {
>

vandana.kannan@intel.com June 3, 2015, 6:31 a.m. UTC | #2

On 5/26/2015 5:50 PM, Sonika Jindal wrote:
> BXT supports following intermediate link rates for edp:
> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
> Adding support for programming the intermediate rates.
>
> v2: Adding clock in bxt_clk_div struct and then look for the entry with
> required rate (Ville)
> v3: 'clock' has the selected value, no need to use link_bw or rate_select
> for selecting pll(Ville)
> v4: Make bxt_dp_clk_val const and remove size (Ville)
> v5: Rebased
> v6: Removed setting of vco while rebasing in v5, adding it back
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>(v4)
> ---
>   drivers/gpu/drm/i915/intel_ddi.c |   39 ++++++++++++++++----------------------
>   drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>   2 files changed, 22 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cacb07b..2a2518d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>
>   /* bxt clock parameters */
>   struct bxt_clk_div {
> +	int clock;
>   	uint32_t p1;
>   	uint32_t p2;
>   	uint32_t m2_int;
> @@ -1343,14 +1344,14 @@ struct bxt_clk_div {
>   };
>
>   /* pre-calculated values for DP linkrates */
> -static struct bxt_clk_div bxt_dp_clk_val[7] = {
> -	/* 162 */ {4, 2, 32, 1677722, 1, 1},
> -	/* 270 */ {4, 1, 27,       0, 0, 1},
> -	/* 540 */ {2, 1, 27,       0, 0, 1},
> -	/* 216 */ {3, 2, 32, 1677722, 1, 1},
> -	/* 243 */ {4, 1, 24, 1258291, 1, 1},
> -	/* 324 */ {4, 1, 32, 1677722, 1, 1},
> -	/* 432 */ {3, 1, 32, 1677722, 1, 1}
> +static const struct bxt_clk_div bxt_dp_clk_val[] = {
> +	{162000, 4, 2, 32, 1677722, 1, 1},
> +	{270000, 4, 1, 27,       0, 0, 1},
> +	{540000, 2, 1, 27,       0, 0, 1},
> +	{216000, 3, 2, 32, 1677722, 1, 1},
> +	{243000, 4, 1, 24, 1258291, 1, 1},
> +	{324000, 4, 1, 32, 1677722, 1, 1},
> +	{432000, 3, 1, 32, 1677722, 1, 1}
>   };
>
>   static bool
> @@ -1390,22 +1391,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>   		vco = best_clock.vco;
>   	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>   			intel_encoder->type == INTEL_OUTPUT_EDP) {
> -		struct drm_encoder *encoder = &intel_encoder->base;
> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +		int i;
>
> -		switch (intel_dp->link_bw) {
> -		case DP_LINK_BW_1_62:
> -			clk_div = bxt_dp_clk_val[0];
> -			break;
> -		case DP_LINK_BW_2_7:
> -			clk_div = bxt_dp_clk_val[1];
> -			break;
> -		case DP_LINK_BW_5_4:
> -			clk_div = bxt_dp_clk_val[2];
> -			break;
> -		default:
> -			clk_div = bxt_dp_clk_val[0];
> -			DRM_ERROR("Unknown link rate\n");
> +		clk_div = bxt_dp_clk_val[0];
> +		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
> +			if (bxt_dp_clk_val[i].clock == clock) {
> +				clk_div = bxt_dp_clk_val[i];
> +				break;
> +			}
>   		}
>   		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>   	}
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index abd442a..bd0f958 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>   };
>
> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
> +				  324000, 432000, 540000 };
>   static const int skl_rates[] = { 162000, 216000, 270000,
>   				  324000, 432000, 540000 };
>   static const int chv_rates[] = { 162000, 202500, 210000, 216000,
> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>   static int
>   intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>   {
> -	if (IS_SKYLAKE(dev)) {
> +	if (IS_BROXTON(dev)) {
> +		*source_rates = bxt_rates;
> +		return ARRAY_SIZE(bxt_rates);
> +	} else if (IS_SKYLAKE(dev)) {
>   		*source_rates = skl_rates;
>   		return ARRAY_SIZE(skl_rates);
>   	} else if (IS_CHERRYVIEW(dev)) {
>
Reviewed-by: Vandana Kannan <vandana.kannan@intel.com>

Jani Nikula June 3, 2015, 8 a.m. UTC | #3

On Wed, 03 Jun 2015, "Kannan, Vandana" <vandana.kannan@intel.com> wrote:
> On 5/26/2015 5:50 PM, Sonika Jindal wrote:
>> BXT supports following intermediate link rates for edp:
>> 2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
>> Adding support for programming the intermediate rates.
>>
>> v2: Adding clock in bxt_clk_div struct and then look for the entry with
>> required rate (Ville)
>> v3: 'clock' has the selected value, no need to use link_bw or rate_select
>> for selecting pll(Ville)
>> v4: Make bxt_dp_clk_val const and remove size (Ville)
>> v5: Rebased
>> v6: Removed setting of vco while rebasing in v5, adding it back
>>
>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>(v4)

Pushed to drm-intel-next-queued, thanks for the patch and review.

BR,
Jani.

>> ---
>>   drivers/gpu/drm/i915/intel_ddi.c |   39 ++++++++++++++++----------------------
>>   drivers/gpu/drm/i915/intel_dp.c  |    7 ++++++-
>>   2 files changed, 22 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index cacb07b..2a2518d 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -1334,6 +1334,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
>>
>>   /* bxt clock parameters */
>>   struct bxt_clk_div {
>> +	int clock;
>>   	uint32_t p1;
>>   	uint32_t p2;
>>   	uint32_t m2_int;
>> @@ -1343,14 +1344,14 @@ struct bxt_clk_div {
>>   };
>>
>>   /* pre-calculated values for DP linkrates */
>> -static struct bxt_clk_div bxt_dp_clk_val[7] = {
>> -	/* 162 */ {4, 2, 32, 1677722, 1, 1},
>> -	/* 270 */ {4, 1, 27,       0, 0, 1},
>> -	/* 540 */ {2, 1, 27,       0, 0, 1},
>> -	/* 216 */ {3, 2, 32, 1677722, 1, 1},
>> -	/* 243 */ {4, 1, 24, 1258291, 1, 1},
>> -	/* 324 */ {4, 1, 32, 1677722, 1, 1},
>> -	/* 432 */ {3, 1, 32, 1677722, 1, 1}
>> +static const struct bxt_clk_div bxt_dp_clk_val[] = {
>> +	{162000, 4, 2, 32, 1677722, 1, 1},
>> +	{270000, 4, 1, 27,       0, 0, 1},
>> +	{540000, 2, 1, 27,       0, 0, 1},
>> +	{216000, 3, 2, 32, 1677722, 1, 1},
>> +	{243000, 4, 1, 24, 1258291, 1, 1},
>> +	{324000, 4, 1, 32, 1677722, 1, 1},
>> +	{432000, 3, 1, 32, 1677722, 1, 1}
>>   };
>>
>>   static bool
>> @@ -1390,22 +1391,14 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>>   		vco = best_clock.vco;
>>   	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
>>   			intel_encoder->type == INTEL_OUTPUT_EDP) {
>> -		struct drm_encoder *encoder = &intel_encoder->base;
>> -		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +		int i;
>>
>> -		switch (intel_dp->link_bw) {
>> -		case DP_LINK_BW_1_62:
>> -			clk_div = bxt_dp_clk_val[0];
>> -			break;
>> -		case DP_LINK_BW_2_7:
>> -			clk_div = bxt_dp_clk_val[1];
>> -			break;
>> -		case DP_LINK_BW_5_4:
>> -			clk_div = bxt_dp_clk_val[2];
>> -			break;
>> -		default:
>> -			clk_div = bxt_dp_clk_val[0];
>> -			DRM_ERROR("Unknown link rate\n");
>> +		clk_div = bxt_dp_clk_val[0];
>> +		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
>> +			if (bxt_dp_clk_val[i].clock == clock) {
>> +				clk_div = bxt_dp_clk_val[i];
>> +				break;
>> +			}
>>   		}
>>   		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>>   	}
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index abd442a..bd0f958 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -91,6 +91,8 @@ static const struct dp_link_dpll chv_dpll[] = {
>>   		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
>>   };
>>
>> +static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
>> +				  324000, 432000, 540000 };
>>   static const int skl_rates[] = { 162000, 216000, 270000,
>>   				  324000, 432000, 540000 };
>>   static const int chv_rates[] = { 162000, 202500, 210000, 216000,
>> @@ -1170,7 +1172,10 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>>   static int
>>   intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
>>   {
>> -	if (IS_SKYLAKE(dev)) {
>> +	if (IS_BROXTON(dev)) {
>> +		*source_rates = bxt_rates;
>> +		return ARRAY_SIZE(bxt_rates);
>> +	} else if (IS_SKYLAKE(dev)) {
>>   		*source_rates = skl_rates;
>>   		return ARRAY_SIZE(skl_rates);
>>   	} else if (IS_CHERRYVIEW(dev)) {
>>
> Reviewed-by: Vandana Kannan <vandana.kannan@intel.com>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cacb07b..2a2518d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1334,6 +1334,7 @@  skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 
 /* bxt clock parameters */
 struct bxt_clk_div {
+	int clock;
 	uint32_t p1;
 	uint32_t p2;
 	uint32_t m2_int;
@@ -1343,14 +1344,14 @@  struct bxt_clk_div {
 };
 
 /* pre-calculated values for DP linkrates */
-static struct bxt_clk_div bxt_dp_clk_val[7] = {
-	/* 162 */ {4, 2, 32, 1677722, 1, 1},
-	/* 270 */ {4, 1, 27,       0, 0, 1},
-	/* 540 */ {2, 1, 27,       0, 0, 1},
-	/* 216 */ {3, 2, 32, 1677722, 1, 1},
-	/* 243 */ {4, 1, 24, 1258291, 1, 1},
-	/* 324 */ {4, 1, 32, 1677722, 1, 1},
-	/* 432 */ {3, 1, 32, 1677722, 1, 1}
+static const struct bxt_clk_div bxt_dp_clk_val[] = {
+	{162000, 4, 2, 32, 1677722, 1, 1},
+	{270000, 4, 1, 27,       0, 0, 1},
+	{540000, 2, 1, 27,       0, 0, 1},
+	{216000, 3, 2, 32, 1677722, 1, 1},
+	{243000, 4, 1, 24, 1258291, 1, 1},
+	{324000, 4, 1, 32, 1677722, 1, 1},
+	{432000, 3, 1, 32, 1677722, 1, 1}
 };
 
 static bool
@@ -1390,22 +1391,14 @@  bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
 		vco = best_clock.vco;
 	} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 			intel_encoder->type == INTEL_OUTPUT_EDP) {
-		struct drm_encoder *encoder = &intel_encoder->base;
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+		int i;
 
-		switch (intel_dp->link_bw) {
-		case DP_LINK_BW_1_62:
-			clk_div = bxt_dp_clk_val[0];
-			break;
-		case DP_LINK_BW_2_7:
-			clk_div = bxt_dp_clk_val[1];
-			break;
-		case DP_LINK_BW_5_4:
-			clk_div = bxt_dp_clk_val[2];
-			break;
-		default:
-			clk_div = bxt_dp_clk_val[0];
-			DRM_ERROR("Unknown link rate\n");
+		clk_div = bxt_dp_clk_val[0];
+		for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
+			if (bxt_dp_clk_val[i].clock == clock) {
+				clk_div = bxt_dp_clk_val[i];
+				break;
+			}
 		}
 		vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
 	}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index abd442a..bd0f958 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -91,6 +91,8 @@  static const struct dp_link_dpll chv_dpll[] = {
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 
+static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
+				  324000, 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 				  324000, 432000, 540000 };
 static const int chv_rates[] = { 162000, 202500, 210000, 216000,
@@ -1170,7 +1172,10 @@  intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
 {
-	if (IS_SKYLAKE(dev)) {
+	if (IS_BROXTON(dev)) {
+		*source_rates = bxt_rates;
+		return ARRAY_SIZE(bxt_rates);
+	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		return ARRAY_SIZE(skl_rates);
 	} else if (IS_CHERRYVIEW(dev)) {

drm/i915/bxt: edp1.4 Intermediate Freq support

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