diff mbox

[2/2] drm/i915/skl: Add debug messages at the start/end of DMC firmware loading

Message ID 1433432536-605-2-git-send-email-damien.lespiau@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lespiau, Damien June 4, 2015, 3:42 p.m. UTC
It's handy to have debug message for the "big" events and this one
qualifies IMHO. Also helpful to see what's happening while we're loading
the firwmare and how much time it takes.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Chris Wilson June 4, 2015, 3:47 p.m. UTC | #1
On Thu, Jun 04, 2015 at 04:42:16PM +0100, Damien Lespiau wrote:
> It's handy to have debug message for the "big" events and this one
> qualifies IMHO. Also helpful to see what's happening while we're loading
> the firwmare and how much time it takes.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_csr.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index aae0652..2cf25ee 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -389,6 +389,7 @@ static void finish_csr_load(const struct firmware *fw, void *context)
>  	intel_csr_load_program(dev);
>  	fw_loaded = true;
>  
> +	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);

KMS? DRM_DEBUG_DRIVER() as it is off wider scope.
-Chris
Lespiau, Damien June 4, 2015, 5:10 p.m. UTC | #2
On Thu, Jun 04, 2015 at 04:47:00PM +0100, Chris Wilson wrote:
> On Thu, Jun 04, 2015 at 04:42:16PM +0100, Damien Lespiau wrote:
> > It's handy to have debug message for the "big" events and this one
> > qualifies IMHO. Also helpful to see what's happening while we're loading
> > the firwmare and how much time it takes.
> > 
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_csr.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> > index aae0652..2cf25ee 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -389,6 +389,7 @@ static void finish_csr_load(const struct firmware *fw, void *context)
> >  	intel_csr_load_program(dev);
> >  	fw_loaded = true;
> >  
> > +	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
> 
> KMS? DRM_DEBUG_DRIVER() as it is off wider scope.

Is it? AFAIK the DMC is all about saving/restoring display registers
when we toggle the power wells between frame updates for eDP + PSR
panels.

But then I guess the loading itself is a generic driver function.
Shuang He June 5, 2015, 1:01 p.m. UTC | #3
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6537
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  270/270              270/270
ILK                                  303/303              303/303
SNB                                  312/312              312/312
IVB                                  343/343              343/343
BYT                                  287/287              287/287
BDW                                  318/318              318/318
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
Daniel Vetter June 15, 2015, 12:31 p.m. UTC | #4
On Thu, Jun 04, 2015 at 06:10:04PM +0100, Damien Lespiau wrote:
> On Thu, Jun 04, 2015 at 04:47:00PM +0100, Chris Wilson wrote:
> > On Thu, Jun 04, 2015 at 04:42:16PM +0100, Damien Lespiau wrote:
> > > It's handy to have debug message for the "big" events and this one
> > > qualifies IMHO. Also helpful to see what's happening while we're loading
> > > the firwmare and how much time it takes.
> > > 
> > > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_csr.c | 3 +++
> > >  1 file changed, 3 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> > > index aae0652..2cf25ee 100644
> > > --- a/drivers/gpu/drm/i915/intel_csr.c
> > > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > > @@ -389,6 +389,7 @@ static void finish_csr_load(const struct firmware *fw, void *context)
> > >  	intel_csr_load_program(dev);
> > >  	fw_loaded = true;
> > >  
> > > +	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
> > 
> > KMS? DRM_DEBUG_DRIVER() as it is off wider scope.
> 
> Is it? AFAIK the DMC is all about saving/restoring display registers
> when we toggle the power wells between frame updates for eDP + PSR
> panels.
> 
> But then I guess the loading itself is a generic driver function.

Well I merged both patches. Someone still owes me the conversion to
refcount away from the hand-rolled completion though ;-)
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index aae0652..2cf25ee 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -389,6 +389,7 @@  static void finish_csr_load(const struct firmware *fw, void *context)
 	intel_csr_load_program(dev);
 	fw_loaded = true;
 
+	DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
 out:
 	if (fw_loaded)
 		intel_runtime_pm_put(dev_priv);
@@ -422,6 +423,8 @@  void intel_csr_ucode_init(struct drm_device *dev)
 		return;
 	}
 
+	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
+
 	/*
 	 * Obtain a runtime pm reference, until CSR is loaded,
 	 * to avoid entering runtime-suspend.