| Message ID | 1433500446-26929-5-git-send-email-arun.siluvery@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 05/06/15 11:34, Arun Siluvery wrote: > In Indirect context w/a batch buffer, > +WaFlushCoherentL3CacheLinesAtContextSwitch > > Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++++ > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 84af255..5203c79 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -426,6 +426,7 @@ > #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) > #define PIPE_CONTROL_NOTIFY (1<<8) > #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ > +#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) > #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) > #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) > #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 2fdb3da..5b6c9db 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1102,6 +1102,14 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring) > /* WaDisableCtxRestoreArbitration:bdw,chv */ > reg_state[index++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; > > + /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw,chv */ > + reg_state[index++] = GFX_OP_PIPE_CONTROL(6); > + reg_state[index++] = PIPE_CONTROL_DC_FLUSH_ENABLE; > + reg_state[index++] = 0; > + reg_state[index++] = 0; > + reg_state[index++] = 0; > + reg_state[index++] = 0; Is DC_FLUSH valid without setting the CS_STALL bit? .Dave.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 84af255..5203c79 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -426,6 +426,7 @@ #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) #define PIPE_CONTROL_NOTIFY (1<<8) #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ +#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 2fdb3da..5b6c9db 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1102,6 +1102,14 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring) /* WaDisableCtxRestoreArbitration:bdw,chv */ reg_state[index++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; + /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw,chv */ + reg_state[index++] = GFX_OP_PIPE_CONTROL(6); + reg_state[index++] = PIPE_CONTROL_DC_FLUSH_ENABLE; + reg_state[index++] = 0; + reg_state[index++] = 0; + reg_state[index++] = 0; + reg_state[index++] = 0; + /* padding */ while (index < end) reg_state[index++] = MI_NOOP;