From patchwork Thu Jun 11 19:02:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paulo Zanoni X-Patchwork-Id: 6591201 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A9030C0020 for ; Thu, 11 Jun 2015 19:03:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E941020616 for ; Thu, 11 Jun 2015 19:03:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 19F2C2062F for ; Thu, 11 Jun 2015 19:03:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A13996E56B; Thu, 11 Jun 2015 12:03:35 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-qg0-f67.google.com (mail-qg0-f67.google.com [209.85.192.67]) by gabe.freedesktop.org (Postfix) with ESMTP id DFF616E56B for ; Thu, 11 Jun 2015 12:03:33 -0700 (PDT) Received: by qgdq107 with SMTP id q107so1821824qgd.2 for ; Thu, 11 Jun 2015 12:03:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4QL4+oHy3zRC3Z9dVaxJGhCfuh6fmFqwFKphfkVHEx4=; b=Cqg5+pPaTDJeKNf5ghvtpQXKo8AT4H+nsEAxmfHFxHtLfM+u6GhEfHllQcalhV8jmu 0abPhISrEbR9sqN2V2K27bWxNQTEe/FaX/Rs865r/aySs05qEI/5jFNsdi4wUgB9BGQT Z7ARFodKUvwJYcmv4037S0t2SsQOSGmT2vzmunVPza7nb96SF+tvdNF+yXMoI9tAnRWp GDl31/9RwgsT4Ig1klnvRTbjpgCSmHIC525SktjjDVgQVLsGau9FWd9QvVmo0ts/bUYf djvas+p0ttLcRxBXS8RSlG8tq8BXQUS4HOqtdCrJwUwineZCIBRHdbiRNqjsR8wxoCKS qLPA== X-Received: by 10.55.40.66 with SMTP id o63mr22561894qkh.47.1434049413502; Thu, 11 Jun 2015 12:03:33 -0700 (PDT) Received: from localhost.localdomain ([187.95.117.237]) by mx.google.com with ESMTPSA id j143sm626145qhc.32.2015.06.11.12.03.31 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 11 Jun 2015 12:03:32 -0700 (PDT) From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Thu, 11 Jun 2015 16:02:27 -0300 Message-Id: <1434049347-2100-5-git-send-email-przanoni@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1434049347-2100-1-git-send-email-przanoni@gmail.com> References: <1434049347-2100-1-git-send-email-przanoni@gmail.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 4/4] drm/i915: don't set the FBC plane select bits on HSW+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni This commit is just to make the intentions explicit: on HSW+ these bits are MBZ, but since we only support plane A and the macro evaluates to zero when plane A is the parameter, we're not fixing any bug. Signed-off-by: Paulo Zanoni Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/intel_fbc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 9b300bd..8b980e5 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -258,11 +258,14 @@ static void gen7_fbc_enable(struct drm_crtc *crtc) struct drm_framebuffer *fb = crtc->primary->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct intel_crtc *intel_crtc = to_intel_crtc(crtc); - u32 dpfc_ctl; + u32 dpfc_ctl = 0; dev_priv->fbc.enabled = true; - dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); + + if (IS_IVYBRIDGE(dev)) + dpfc_ctl |= IVB_DPFC_CTL_PLANE(intel_crtc->plane); + if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) dev_priv->fbc.threshold++;