From patchwork Mon Jun 15 18:36:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gordon X-Patchwork-Id: 6611301 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6B1FC9F1C1 for ; Mon, 15 Jun 2015 18:38:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6123620414 for ; Mon, 15 Jun 2015 18:38:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2F7B520279 for ; Mon, 15 Jun 2015 18:38:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 939116E894; Mon, 15 Jun 2015 11:38:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 52BDD6E894 for ; Mon, 15 Jun 2015 11:38:13 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 15 Jun 2015 11:38:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,620,1427785200"; d="scan'208";a="747116631" Received: from dsgordon-linux.isw.intel.com ([10.102.226.51]) by orsmga002.jf.intel.com with ESMTP; 15 Jun 2015 11:38:11 -0700 From: Dave Gordon To: intel-gfx@lists.freedesktop.org Date: Mon, 15 Jun 2015 19:36:25 +0100 Message-Id: <1434393394-21002-8-git-send-email-david.s.gordon@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1434393394-21002-1-git-send-email-david.s.gordon@intel.com> References: <1434393394-21002-1-git-send-email-david.s.gordon@intel.com> Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ Subject: [Intel-gfx] [PATCH 07/15] drm/i915: Defer default hardware context initialisation until first open X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to fully initialise the default contexts, we have to execute batchbuffer commands on the GPU engines. But in the case of GuC-based batch submission, we can't do that until any required firmware has been loaded, which may not be possible during driver load, because the filesystem(s) containing the firmware may not be mounted until later. Therefore, we now allow the first call to the firmware-loading code to return -EAGAIN to indicate that it's not yet ready, and that it should be retried when the device is first opened from user code, by which time we expect that all required filesystems will have been mounted. The late-retry code will then re-attempt to load the firmware if the early attempt failed. If the late retry fails, the current open-in-progress will fail, but the recovery code will disable GuC submission and reset the GPU and driver. The next open will therefore be in non-GuC mode, and will be allowed to complete even if the GuC cannot be loaded or used. Issue: VIZ-4884 Signed-off-by: Dave Gordon Signed-off-by: Alex Dai --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 9 +++++- drivers/gpu/drm/i915/i915_gem_context.c | 52 ++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_irq.c | 48 ++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f47cde7..a1fc278 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1837,6 +1837,7 @@ struct drm_i915_private { /* hda/i915 audio component */ bool audio_component_registered; + bool contexts_ready; uint32_t hw_context_size; struct list_head context_list; @@ -2614,6 +2615,7 @@ void i915_queue_hangcheck(struct drm_device *dev); __printf(3, 4) void i915_handle_error(struct drm_device *dev, bool wedged, const char *fmt, ...); +void i915_handle_guc_error(struct drm_device *dev, int err); extern void intel_irq_init(struct drm_i915_private *dev_priv); extern void intel_hpd_init(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index cd4a865..d1a8862 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5025,8 +5025,15 @@ i915_gem_init_hw(struct drm_device *dev) /* We can't enable contexts until all firmware is loaded */ ret = intel_guc_ucode_load(dev, false); + if (ret == -EAGAIN) { + ret = 0; + goto out; /* too early */ + } + ret = i915_gem_context_enable(dev_priv); - if (ret && ret != -EIO) { + if (ret == 0) { + dev_priv->contexts_ready = true; + } else if (ret && ret != -EIO) { DRM_ERROR("Context enable failed %d\n", ret); i915_gem_cleanup_ringbuffer(dev); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 133afcf..debbfc9 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -447,23 +447,65 @@ static int context_idr_cleanup(int id, void *p, void *data) return 0; } +/* Complete any late initialisation here */ +static int i915_gem_context_first_open(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int ret; + + /* + * We can't enable contexts until all firmware is loaded. This + * call shouldn't return -EAGAIN because we pass wait=true, but + * it can still fail with code -EIO if the GuC doesn't respond, + * or -ENOEXEC if the GuC firmware image is invalid. + */ + ret = intel_guc_ucode_load(dev, true); + WARN_ON(ret == -EAGAIN); + + /* + * If an error occurred and GuC submission has been requested, we can + * attempt recovery by disabling GuC submission and reinitialising + * the GPU and driver. We then fail this open() anyway, but the next + * attempt will find that GuC submission is already disabled, and so + * proceed to complete context initialisation in non-GuC mode instead. + */ + if (ret && i915.enable_guc_submission) { + i915_handle_guc_error(dev, ret); + return ret; + } + + ret = i915_gem_context_enable(dev_priv); + if (ret == 0) + dev_priv->contexts_ready = true; + return ret; +} + int i915_gem_context_open(struct drm_device *dev, struct drm_file *file) { + struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_file_private *file_priv = file->driver_priv; struct intel_context *ctx; + int ret = 0; idr_init(&file_priv->context_idr); mutex_lock(&dev->struct_mutex); - ctx = i915_gem_create_context(dev, file_priv); + + if (!dev_priv->contexts_ready) + ret = i915_gem_context_first_open(dev); + + if (ret == 0) { + ctx = i915_gem_create_context(dev, file_priv); + if (IS_ERR(ctx)) + ret = PTR_ERR(ctx); + } + mutex_unlock(&dev->struct_mutex); - if (IS_ERR(ctx)) { + if (ret) idr_destroy(&file_priv->context_idr); - return PTR_ERR(ctx); - } - return 0; + return ret; } void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 56db9e74..f7dcf8d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2665,6 +2665,54 @@ void i915_handle_error(struct drm_device *dev, bool wedged, i915_reset_and_wakeup(dev); } +/** + * i915_handle_error - handle a GuC error + * @dev: drm device + * + * If the GuC can't be (re-)initialised, disable GuC submission and + * then reset and reinitialise the rest of the GPU, so that we can + * fall back to operating in ELSP mode. Don't bother capturing error + * state, because it probably isn't relevant here. + * + * Unlike i915_handle_error() above, this is called with the global + * struct_mutex held, so we need to release it after setting the + * reset-in-progress bit so that other threads can make progress, + * and reacquire it after the reset is complete. + */ +void i915_handle_guc_error(struct drm_device *dev, int err) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + DRM_ERROR("GuC failure %d, disabling GuC submission\n", err); + i915.enable_guc_submission = false; + + i915_report_and_clear_eir(dev); /* unlikely? */ + + atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, + &dev_priv->gpu_error.reset_counter); + + mutex_unlock(&dev->struct_mutex); + + /* + * Wakeup waiting processes so that the reset function + * i915_reset_and_wakeup doesn't deadlock trying to grab + * various locks. By bumping the reset counter first, the woken + * processes will see a reset in progress and back off, + * releasing their locks and then wait for the reset completion. + * We must do this for _all_ gpu waiters that might hold locks + * that the reset work needs to acquire. + * + * Note: The wake_up serves as the required memory barrier to + * ensure that the waiters see the updated value of the reset + * counter atomic_t. + */ + i915_error_wake_up(dev_priv, false); + + i915_reset_and_wakeup(dev); + + mutex_lock(&dev->struct_mutex); +} + /* Called from drm generic code, passed 'crtc' which * we use as a pipe index */