From patchwork Tue Jun 16 19:25:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 6619771 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 83992C0434 for ; Tue, 16 Jun 2015 19:25:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 88C1520813 for ; Tue, 16 Jun 2015 19:25:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7B80B2078B for ; Tue, 16 Jun 2015 19:25:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 622FC6E560; Tue, 16 Jun 2015 12:25:38 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 51B5D6E55E for ; Tue, 16 Jun 2015 12:25:35 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 16 Jun 2015 12:25:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,627,1427785200"; d="scan'208";a="728659718" Received: from asiluver-linux.isw.intel.com ([10.102.226.85]) by fmsmga001.fm.intel.com with ESMTP; 16 Jun 2015 12:25:34 -0700 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Tue, 16 Jun 2015 20:25:24 +0100 Message-Id: <1434482725-21823-6-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1434482725-21823-1-git-send-email-arun.siluvery@linux.intel.com> References: <1434482725-21823-1-git-send-email-arun.siluvery@linux.intel.com> Subject: [Intel-gfx] [PATCH v4 5/6] drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In Indirect context w/a batch buffer, WaClearSlmSpaceAtContextSwitch v2: s/PIPE_CONTROL_FLUSH_RO_CACHES/PIPE_CONTROL_FLUSH_L3 (Ville) Signed-off-by: Rafael Barbalho Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d14ad20..7637e64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -410,6 +410,7 @@ #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) +#define PIPE_CONTROL_FLUSH_L3 (1<<27) #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ #define PIPE_CONTROL_MMIO_WRITE (1<<23) #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 92556b9..27e6692 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1085,6 +1085,8 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, uint32_t index; struct page *page; uint32_t *cmd; + u32 scratch_addr; + unsigned long flags = 0; page = i915_gem_object_get_page(ring->wa_ctx.obj, 0); cmd = kmap_atomic(page); @@ -1117,6 +1119,23 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, ~GEN8_LQSC_FLUSH_COHERENT_LINES; } + /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ + flags = PIPE_CONTROL_FLUSH_L3 | + PIPE_CONTROL_GLOBAL_GTT_IVB | + PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_QW_WRITE; + + /* Actual scratch location is at 128 bytes offset */ + scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES; + scratch_addr |= PIPE_CONTROL_GLOBAL_GTT; + + cmd[index++] = GFX_OP_PIPE_CONTROL(6); + cmd[index++] = flags; + cmd[index++] = scratch_addr; + cmd[index++] = 0; + cmd[index++] = 0; + cmd[index++] = 0; + /* padding */ while (((unsigned long) (cmd + index) % CACHELINE_BYTES) != 0) cmd[index++] = MI_NOOP;