From patchwork Mon Jun 22 09:55:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sourab.gupta@intel.com X-Patchwork-Id: 6654501 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A2001C05AC for ; Mon, 22 Jun 2015 09:53:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DB989203C0 for ; Mon, 22 Jun 2015 09:53:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EF903203AE for ; Mon, 22 Jun 2015 09:53:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 722E46E5CE; Mon, 22 Jun 2015 02:53:11 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id D89A57206B for ; Mon, 22 Jun 2015 02:53:10 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 22 Jun 2015 02:53:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,658,1427785200"; d="scan'208";a="732124293" Received: from sourabgu-desktop.iind.intel.com ([10.223.82.35]) by fmsmga001.fm.intel.com with ESMTP; 22 Jun 2015 02:53:08 -0700 From: sourab.gupta@intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Jun 2015 15:25:03 +0530 Message-Id: <1434966909-4113-2-git-send-email-sourab.gupta@intel.com> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <1434966909-4113-1-git-send-email-sourab.gupta@intel.com> References: <1434966909-4113-1-git-send-email-sourab.gupta@intel.com> Cc: Insoo Woo , Peter Zijlstra , Jabin Wu , Sourab Gupta Subject: [Intel-gfx] [RFC 1/7] drm/i915: Add a new PMU for handling non-OA counter data profiling requests X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sourab Gupta The current perf PMU driver is specific for collection of OA counter statistics (which may be done in a periodic or asynchronous way). Since this enables us (and limits us) to render ring, we have no means for collection of data pertaining to other rings. To overcome this limitation, we need to have a new PMU driver which enables data collection for other rings also (in a non-OA specific mode). This patch adds a new perf PMU to i915 device private, for handling profiling requests for non-OA counter data.This data may encompass timestamps, mmio register values, etc. for the relevant ring. The new perf PMU will serve these purposes, without constraining itself to type of data being dumped (which may constraint the user to specific ring like in case of OA counters). Signed-off-by: Sourab Gupta --- drivers/gpu/drm/i915/i915_drv.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 758d924..b8b5455 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1985,6 +1985,22 @@ struct drm_i915_private { struct completion complete; } oa_pmu; + struct { + struct pmu pmu; + spinlock_t lock; + struct hrtimer timer; + struct pt_regs dummy_regs; + struct perf_event *exclusive_event; + bool event_active; + + struct { + struct drm_i915_gem_object *obj; + u8 *addr; + u32 head; + u32 tail; + } buffer; + } gen_pmu; + struct list_head profile_cmd; #endif