From patchwork Mon Jun 22 18:47:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anuj Phogat X-Patchwork-Id: 6657431 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8E3B59F1C1 for ; Mon, 22 Jun 2015 18:48:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9A4ED205E1 for ; Mon, 22 Jun 2015 18:48:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9AABF205EA for ; Mon, 22 Jun 2015 18:48:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FCAD6E041; Mon, 22 Jun 2015 11:48:54 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pa0-f42.google.com (mail-pa0-f42.google.com [209.85.220.42]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E5F16E041 for ; Mon, 22 Jun 2015 11:48:53 -0700 (PDT) Received: by pactm7 with SMTP id tm7so468400pac.2 for ; Mon, 22 Jun 2015 11:48:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ywywiUM6FVxusAMof/2JzGgd+/8qJAFaUjMVSSywIcM=; b=wbPL/evkhAfLIv0RG6SQgVFikylMY/Os7kSxLXWCDhAShMVv6CW5erZisi+nfQKqcy LdZ588KL2ESjLuGXA3sZBFWQCQ/S6eC9JWHE8vLNbDC3SXQ4dTvWbYg6gv/jNu+XtGbY LicqzGmqYSMSjL3PZQ/GGfol9fTgijVCoBEZm3UHXakz2xyT7So6xxec9i26EzlzvvcX JoG1gvkwPFwSosX8exl8mjSodVh8Xtfa/tF4D1xskjcFkb3BMZ2VcoknB0Jizqc1sFSr 3fctfOKSJ3m7XY/TFYOI0WRGTV3B2fXJaj6HjQXBUX6bGVQL63K6hKThyRhHxBjwcZQI d0bg== X-Received: by 10.68.99.197 with SMTP id es5mr62063949pbb.131.1434998932880; Mon, 22 Jun 2015 11:48:52 -0700 (PDT) Received: from carbon.ak.intel.com (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by mx.google.com with ESMTPSA id k5sm20653883pdn.10.2015.06.22.11.48.51 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Jun 2015 11:48:52 -0700 (PDT) From: Anuj Phogat To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Jun 2015 11:47:02 -0700 Message-Id: <1434998822-11855-1-git-send-email-anuj.phogat@gmail.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1428711656-5878-1-git-send-email-anuj.phogat@gmail.com> References: <1428711656-5878-1-git-send-email-anuj.phogat@gmail.com> Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH v2 1/2] i965/gen9: Pass alignment as function parameter in drm_intel_gem_bo_alloc_internal() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP and use it to initialize the align variable in drm_intel_bo. In case of YF/YS tiled buffers libdrm need not know about the tiling format because these buffers don't have hardware support to be tiled or detiled through a fenced region. But, libdrm still need to know about buffer alignment restrictions because kernel uses it when resolving the relocation. Mesa uses drm_intel_gem_bo_alloc_for_render() to allocate Yf/Ys buffers. So, use the passed alignment value in this function. Note that we continue ignoring the alignment value passed to drm_intel_gem_bo_alloc() to follow the previous behavior. V2: Add a condition to avoid allocation from cache. (Ben) Signed-off-by: Anuj Phogat Cc: Ben Widawsky --- intel/intel_bufmgr_gem.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 60c06fc..60f494e 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -660,7 +660,8 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, unsigned long size, unsigned long flags, uint32_t tiling_mode, - unsigned long stride) + unsigned long stride, + unsigned int alignment) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; drm_intel_bo_gem *bo_gem; @@ -700,9 +701,14 @@ retry: */ bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.prev, head); - DRMLISTDEL(&bo_gem->head); - alloc_from_cache = true; + if (alignment > 0 && bo_gem->bo.align != alignment) { + alloc_from_cache = false; + } else { + alloc_from_cache = true; + DRMLISTDEL(&bo_gem->head); + } } else { + assert(alignment == 0); /* For non-render-target BOs (where we're probably * going to map it first thing in order to fill it * with data), check if the last BO in the cache is @@ -759,6 +765,7 @@ retry: return NULL; } bo_gem->bo.bufmgr = bufmgr; + bo_gem->bo.align = alignment; bo_gem->tiling_mode = I915_TILING_NONE; bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; @@ -802,7 +809,8 @@ drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, { return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, BO_ALLOC_FOR_RENDER, - I915_TILING_NONE, 0); + I915_TILING_NONE, 0, + alignment); } static drm_intel_bo * @@ -812,7 +820,7 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, unsigned int alignment) { return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0, - I915_TILING_NONE, 0); + I915_TILING_NONE, 0, 0); } static drm_intel_bo * @@ -864,7 +872,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, stride = 0; return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags, - tiling, stride); + tiling, stride, 0); } static drm_intel_bo *