| Message ID | 1435062065-19717-1-git-send-email-michel.thierry@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jun 23, 2015 at 01:21:05PM +0100, Michel Thierry wrote: > There are some allocations that must be only referenced by 32-bit > offsets. To limit the chances of having the first 4GB already full, > objects not requiring this workaround use DRM_MM_SEARCH_BELOW/ > DRM_MM_CREATE_TOP flags > > In specific, any resource used with flat/heapless (0x00000000-0xfffff000) > General State Heap (GSH) or Intructions State Heap (ISH) must be in a > 32-bit range, because the General State Offset and Instruction State > Offset are limited to 32-bits. > > Objects must have EXEC_OBJECT_SUPPORTS_48BADDRESS flag to indicate if > they can be allocated above the 32-bit address range. > > v2: Changed flag logic from neeeds_32b, to supports_48b. > v3: Moved 48-bit support flag back to exec_object. (Chris, Daniel) > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Daniel Vetter <daniel@ffwll.ch> > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_gem.c | 19 +++++++++++++++++-- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 +++++++ > include/uapi/drm/i915_drm.h | 3 ++- > 4 files changed, 27 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index a6bc27a..57af235 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2739,6 +2739,7 @@ void i915_gem_vma_destroy(struct i915_vma *vma); > #define PIN_OFFSET_BIAS (1<<3) > #define PIN_USER (1<<4) > #define PIN_UPDATE (1<<5) > +#define PIN_FULL_RANGE (1<<6) > #define PIN_OFFSET_MASK (~4095) > int __must_check > i915_gem_object_pin(struct drm_i915_gem_object *obj, > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index f4ddf6e..db22559 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3669,6 +3669,8 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, > struct drm_i915_private *dev_priv = dev->dev_private; > u32 fence_alignment, unfenced_alignment; > u64 size, fence_size; > + u32 search_flag = DRM_MM_SEARCH_DEFAULT; > + u32 alloc_flag = DRM_MM_CREATE_DEFAULT; > u64 start = > flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; > u64 end = > @@ -3710,6 +3712,19 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, > obj->tiling_mode, > false); > size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; > + > + /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, > + * limit address to 4GB-1 for objects requiring this wa; for > + * others, set alloc flag to TOP. > + */ > + if (USES_FULL_48BIT_PPGTT(dev)) { > + if (flags & PIN_FULL_RANGE) { I wanted this as a separate PIN_FLAG. (a) it is generally useful (for example, I think anything that has PIN_GLOBAL but not PIN_MAPPABLE is a candidate for this flag), but (b) there are bugs in the drm_mm implementation for searching below... > + search_flag = DRM_MM_SEARCH_BELOW; > + alloc_flag = DRM_MM_CREATE_TOP; > + } else { This would be better internally as a PIN_ZONE_4G flag. > + end = ((4ULL << GEN8_PDPE_SHIFT) - 1); end should not be -1 here (or if that is actually required by the hardware -4096). > + } > + } > } > > if (alignment == 0) > @@ -3752,8 +3767,8 @@ search_free: > size, alignment, > obj->cache_level, > start, end, > - DRM_MM_SEARCH_DEFAULT, > - DRM_MM_CREATE_DEFAULT); > + search_flag, > + alloc_flag); > if (ret) { > ret = i915_gem_evict_something(dev, vm, size, alignment, > obj->cache_level, > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > index 3336e1c..ec8c72d 100644 > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > @@ -588,6 +588,9 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, > if (entry->flags & EXEC_OBJECT_NEEDS_GTT) > flags |= PIN_GLOBAL; > > + if (entry->flags & EXEC_OBJECT_SUPPORTS_48BBADDRESS) > + flags |= PIN_FULL_RANGE; flags |= PIN_ZONE_4G; if (entry->flags & EXEC_OBJECT_SUPPORTS_48BBADDRESS) flags &= ~PIN_ZONE_4G; > if (!drm_mm_node_allocated(&vma->node)) { > if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) > flags |= PIN_GLOBAL | PIN_MAPPABLE; if ((flags & PIN_MAPPABLE) == 0) flags |= PIN_HIGH; > @@ -670,6 +673,10 @@ eb_vma_misplaced(struct i915_vma *vma) > if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) > return !only_mappable_for_reloc(entry->flags); > > + if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48BBADDRESS) && > + vma->node.start >= (1ULL << 32)) vma->node.start + vma->node.size > 1<<32 -Chris
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a6bc27a..57af235 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2739,6 +2739,7 @@ void i915_gem_vma_destroy(struct i915_vma *vma); #define PIN_OFFSET_BIAS (1<<3) #define PIN_USER (1<<4) #define PIN_UPDATE (1<<5) +#define PIN_FULL_RANGE (1<<6) #define PIN_OFFSET_MASK (~4095) int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f4ddf6e..db22559 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3669,6 +3669,8 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, struct drm_i915_private *dev_priv = dev->dev_private; u32 fence_alignment, unfenced_alignment; u64 size, fence_size; + u32 search_flag = DRM_MM_SEARCH_DEFAULT; + u32 alloc_flag = DRM_MM_CREATE_DEFAULT; u64 start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; u64 end = @@ -3710,6 +3712,19 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, obj->tiling_mode, false); size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; + + /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset, + * limit address to 4GB-1 for objects requiring this wa; for + * others, set alloc flag to TOP. + */ + if (USES_FULL_48BIT_PPGTT(dev)) { + if (flags & PIN_FULL_RANGE) { + search_flag = DRM_MM_SEARCH_BELOW; + alloc_flag = DRM_MM_CREATE_TOP; + } else { + end = ((4ULL << GEN8_PDPE_SHIFT) - 1); + } + } } if (alignment == 0) @@ -3752,8 +3767,8 @@ search_free: size, alignment, obj->cache_level, start, end, - DRM_MM_SEARCH_DEFAULT, - DRM_MM_CREATE_DEFAULT); + search_flag, + alloc_flag); if (ret) { ret = i915_gem_evict_something(dev, vm, size, alignment, obj->cache_level, diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 3336e1c..ec8c72d 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -588,6 +588,9 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, if (entry->flags & EXEC_OBJECT_NEEDS_GTT) flags |= PIN_GLOBAL; + if (entry->flags & EXEC_OBJECT_SUPPORTS_48BBADDRESS) + flags |= PIN_FULL_RANGE; + if (!drm_mm_node_allocated(&vma->node)) { if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) flags |= PIN_GLOBAL | PIN_MAPPABLE; @@ -670,6 +673,10 @@ eb_vma_misplaced(struct i915_vma *vma) if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) return !only_mappable_for_reloc(entry->flags); + if (!(entry->flags & EXEC_OBJECT_SUPPORTS_48BBADDRESS) && + vma->node.start >= (1ULL << 32)) + return true; + return false; } diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index f88cc1c..55ba527 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -685,7 +685,8 @@ struct drm_i915_gem_exec_object2 { #define EXEC_OBJECT_NEEDS_FENCE (1<<0) #define EXEC_OBJECT_NEEDS_GTT (1<<1) #define EXEC_OBJECT_WRITE (1<<2) -#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) +#define EXEC_OBJECT_SUPPORTS_48BBADDRESS (1<<3) +#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_SUPPORTS_48BBADDRESS<<1) __u64 flags; __u64 rsvd1;
There are some allocations that must be only referenced by 32-bit offsets. To limit the chances of having the first 4GB already full, objects not requiring this workaround use DRM_MM_SEARCH_BELOW/ DRM_MM_CREATE_TOP flags In specific, any resource used with flat/heapless (0x00000000-0xfffff000) General State Heap (GSH) or Intructions State Heap (ISH) must be in a 32-bit range, because the General State Offset and Instruction State Offset are limited to 32-bits. Objects must have EXEC_OBJECT_SUPPORTS_48BADDRESS flag to indicate if they can be allocated above the 32-bit address range. v2: Changed flag logic from neeeds_32b, to supports_48b. v3: Moved 48-bit support flag back to exec_object. (Chris, Daniel) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Michel Thierry <michel.thierry@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 19 +++++++++++++++++-- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 +++++++ include/uapi/drm/i915_drm.h | 3 ++- 4 files changed, 27 insertions(+), 3 deletions(-)