From patchwork Tue Jun 23 12:21:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 6660631 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8983FC05AC for ; Tue, 23 Jun 2015 12:21:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AC55E2068D for ; Tue, 23 Jun 2015 12:21:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B4DE020689 for ; Tue, 23 Jun 2015 12:21:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D3D36E985; Tue, 23 Jun 2015 05:21:19 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 846876E97F; Tue, 23 Jun 2015 05:21:15 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 23 Jun 2015 05:21:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,665,1427785200"; d="scan'208";a="732944067" Received: from michelth-linux.isw.intel.com ([10.102.226.66]) by fmsmga001.fm.intel.com with ESMTP; 23 Jun 2015 05:21:14 -0700 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Tue, 23 Jun 2015 13:21:27 +0100 Message-Id: <1435062089-19877-2-git-send-email-michel.thierry@intel.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1435062089-19877-1-git-send-email-michel.thierry@intel.com> References: <1435062089-19877-1-git-send-email-michel.thierry@intel.com> Cc: mesa-dev@lists.freedesktop.org Subject: [Intel-gfx] [PATCH mesa] i965/gen8+: bo in state base address must be in 32-bit address range X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. In specific, any resource used with flat/heapless (0x00000000-0xfffff000) General State Heap (GSH) or Intruction State Heap (ISH) must be in a 32-bit range, because the General State Offset and Instruction State Offset are limited to 32-bits. Set provided bo flag when the 4GB limit is not necessary, to be able to use the full address space. Cc: mesa-dev@lists.freedesktop.org Signed-off-by: Michel Thierry --- src/mesa/drivers/dri/i965/gen8_misc_state.c | 6 +++--- src/mesa/drivers/dri/i965/intel_batchbuffer.h | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c index b20038e..26531d0 100644 --- a/src/mesa/drivers/dri/i965/gen8_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c @@ -41,17 +41,17 @@ void gen8_upload_state_base_address(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(mocs_wb << 16); /* Surface state base address: */ - OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, + OUT_RELOC64_32BWA(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, mocs_wb << 4 | 1); /* Dynamic state base address: */ - OUT_RELOC64(brw->batch.bo, + OUT_RELOC64_32BWA(brw->batch.bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, mocs_wb << 4 | 1); /* Indirect object base address: MEDIA_OBJECT data */ OUT_BATCH(mocs_wb << 4 | 1); OUT_BATCH(0); /* Instruction base address: shader kernels (incl. SIP) */ - OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + OUT_RELOC64_32BWA(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, mocs_wb << 4 | 1); /* General state buffer size */ diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h index 7bdd836..5aa741e 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h @@ -177,6 +177,13 @@ intel_batchbuffer_advance(struct brw_context *brw) /* Handle 48-bit address relocations for Gen8+ */ #define OUT_RELOC64(buf, read_domains, write_domain, delta) do { \ + drm_intel_bo_set_supports_48baddress(buf); \ + intel_batchbuffer_emit_reloc64(brw, buf, read_domains, write_domain, delta); \ +} while (0) + +/* Handle 48-bit address relocations for Gen8+, ask for 32-bit address */ +#define OUT_RELOC64_32BWA(buf, read_domains, write_domain, delta) do { \ + drm_intel_bo_clear_supports_48baddress(buf); \ intel_batchbuffer_emit_reloc64(brw, buf, read_domains, write_domain, delta); \ } while (0)