From patchwork Fri Jun 26 13:51:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chandra Konduru X-Patchwork-Id: 6681081 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2A4D9C05AC for ; Fri, 26 Jun 2015 13:52:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 05F4D2061D for ; Fri, 26 Jun 2015 13:52:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id AC51720640 for ; Fri, 26 Jun 2015 13:52:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2364F6E062; Fri, 26 Jun 2015 06:52:46 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id B974C6E062 for ; Fri, 26 Jun 2015 06:52:45 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 26 Jun 2015 06:52:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,685,1427785200"; d="scan'208";a="735218504" Received: from cmkondur-desk2.fm.intel.com ([10.1.130.102]) by fmsmga001.fm.intel.com with ESMTP; 26 Jun 2015 06:52:45 -0700 From: Chandra Konduru To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Jun 2015 06:51:41 -0700 Message-Id: <1435326704-12372-2-git-send-email-chandra.konduru@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1435326704-12372-1-git-send-email-chandra.konduru@intel.com> References: <1435326704-12372-1-git-send-email-chandra.konduru@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] =?utf-8?q?=5BPATCH_v4=5D_drm/i915=3A_Add_support_for_?= =?utf-8?q?SKL_background_color?= X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for Skylake display pipe background color. Signed-off-by: Chandra Konduru --- Documentation/DocBook/drm.tmpl | 10 ++++- drivers/gpu/drm/i915/i915_reg.h | 10 +++++ drivers/gpu/drm/i915/intel_display.c | 73 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 2 + include/drm/drm_crtc.h | 3 ++ 5 files changed, 97 insertions(+), 1 deletion(-) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 7d03a74..1f6f4f0 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -2663,7 +2663,7 @@ void intel_crt_init(struct drm_device *dev) TBD - i915 + i915 Generic "Broadcast RGB" ENUM @@ -2687,6 +2687,14 @@ void intel_crt_init(struct drm_device *dev) TBD + CRTC + “background_color” + Range + Min=0, Max=0xFFFFFF + CRTC + Background color in 16bpc BGR (B-MSB, R-LSB) + + SDVO-TV “mode” ENUM diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 84b37d7..795b53f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6579,6 +6579,16 @@ enum kdiv { #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) +/* Skylake pipe bottom color */ +#define _PIPE_BOTTOM_COLOR_A 0x70034 +#define _PIPE_BOTTOM_COLOR_B 0x71034 +#define _PIPE_BOTTOM_COLOR_C 0x72034 +#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31) +#define PIPE_BOTTOM_CSC_ENABLE (1 << 30) +#define PIPE_BOTTOM_COLOR_MASK 0x3FFFFFFF +#define PIPE_BOTTOM_COLOR(pipe) _PIPE3(pipe, _PIPE_BOTTOM_COLOR_A, \ + _PIPE_BOTTOM_COLOR_B, _PIPE_BOTTOM_COLOR_C) + /* VLV MIPI registers */ #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d162dca..d4b7c0c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6951,6 +6951,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) struct intel_crtc *intel_crtc = to_intel_crtc(crtc); int pipe = intel_crtc->pipe; uint16_t coeff = 0x7800; /* 1.0 */ + uint32_t color; /* * TODO: Check what kind of values actually come out of the pipe @@ -6999,6 +7000,14 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc) I915_WRITE(PIPE_CSC_MODE(pipe), mode); } + + /* set csc for bottom color */ + if (INTEL_INFO(dev)->gen >= 9) { + color = I915_READ(PIPE_BOTTOM_COLOR(pipe)); + color |= PIPE_BOTTOM_CSC_ENABLE; + I915_WRITE(PIPE_BOTTOM_COLOR(pipe), color); + intel_crtc->background_color |= PIPE_BOTTOM_CSC_ENABLE; + } } static void haswell_set_pipeconf(struct drm_crtc *crtc) @@ -8568,6 +8577,9 @@ static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, { int end = (start + size > 256) ? 256 : start + size, i; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t color; for (i = start; i < end; i++) { intel_crtc->lut_r[i] = red[i] >> 8; @@ -8576,6 +8588,14 @@ static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, } intel_crtc_load_lut(crtc); + + if (INTEL_INFO(dev)->gen >= 9) { + /* set gamma for bottom color */ + color = I915_READ(PIPE_BOTTOM_COLOR(intel_crtc->pipe)); + color |= PIPE_BOTTOM_GAMMA_ENABLE; + I915_WRITE(PIPE_BOTTOM_COLOR(intel_crtc->pipe), color); + intel_crtc->background_color |= PIPE_BOTTOM_GAMMA_ENABLE; + } } /* VESA 640x480x72Hz mode to set on the pipe */ @@ -9350,6 +9370,12 @@ static void intel_crtc_destroy(struct drm_crtc *crtc) kfree(work); } + if (dev->mode_config.background_color_property) { + drm_property_destroy(crtc->dev, + dev->mode_config.background_color_property); + dev->mode_config.background_color_property = NULL; + } + drm_crtc_cleanup(crtc); kfree(intel_crtc); @@ -10131,6 +10157,33 @@ out_hang: return ret; } +static int intel_crtc_set_property(struct drm_crtc *crtc, + struct drm_property *property, uint64_t val) +{ + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int i; + + if (INTEL_INFO(dev)->gen >= 9) { + if (property == dev->mode_config.background_color_property) { + uint64_t bottom; + bottom = intel_crtc->background_color & ~PIPE_BOTTOM_COLOR_MASK; + + /* BGR 16bpc ==> RGB 10bpc */ + for (i = 0; i < 3; i++) + bottom |= + ((((val >> (i*16)) & 0xFFFF) * 0x3FF/0xFFFF) << ((2-i)*10)); + + I915_WRITE(PIPE_BOTTOM_COLOR(intel_crtc->pipe), (uint32_t) bottom); + intel_crtc->background_color = (uint32_t) bottom; + } + return 0; + } + return -EINVAL; +} + + static struct drm_crtc_helper_funcs intel_helper_funcs = { .mode_set_base_atomic = intel_pipe_set_base_atomic, .load_lut = intel_crtc_load_lut, @@ -11258,6 +11311,11 @@ static int __intel_set_mode(struct drm_crtc *crtc, if (dev_priv->display.modeset_global_resources) dev_priv->display.modeset_global_resources(dev); + /* Set background color */ + if (INTEL_INFO(dev)->gen >= 9) + I915_WRITE(PIPE_BOTTOM_COLOR(to_intel_crtc(crtc)->pipe), + to_intel_crtc(crtc)->background_color); + /* Set up the DPLL and any encoders state that needs to adjust or depend * on the DPLL. */ @@ -11760,6 +11818,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = { .set_config = intel_crtc_set_config, .destroy = intel_crtc_destroy, .page_flip = intel_crtc_page_flip, + .set_property = intel_crtc_set_property, }; static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, @@ -12212,6 +12271,20 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); + + /* background color = 24 bit : MSB BGR 8bpc LSB */ + intel_crtc->background_color = 0; + if (INTEL_INFO(dev)->gen >= 9 && + !dev->mode_config.background_color_property) + dev->mode_config.background_color_property = + drm_property_create_range(dev, 0, "background_color", 0, + 0xFFFFFFFFFFFF); + + if (dev->mode_config.background_color_property) + drm_object_attach_property(&intel_crtc->base.base, + dev->mode_config.background_color_property, + intel_crtc->background_color); + return; fail: diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index c2830d8..0185dbe 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -445,6 +445,8 @@ struct intel_crtc { int scanline_offset; struct intel_mmio_flip mmio_flip; + + uint32_t background_color; }; struct intel_plane_wm_parameters { diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 31344bf..27bcd01 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -827,6 +827,9 @@ struct drm_mode_config { struct drm_property *plane_type_property; struct drm_property *rotation_property; + /* crtc properties */ + struct drm_property *background_color_property; + /* DVI-I properties */ struct drm_property *dvi_i_subconnector_property; struct drm_property *dvi_i_select_subconnector_property;