From patchwork Fri Jun 26 13:51:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 6681151 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 805A6C05AC for ; Fri, 26 Jun 2015 14:00:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 983972049C for ; Fri, 26 Jun 2015 14:00:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id AB15C204A9 for ; Fri, 26 Jun 2015 14:00:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FAE96EC93; Fri, 26 Jun 2015 07:00:03 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 5258C7A140 for ; Fri, 26 Jun 2015 07:00:01 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 26 Jun 2015 07:00:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,685,1427785200"; d="scan'208";a="750977985" Received: from ramaling-desktop.iind.intel.com ([10.223.26.95]) by fmsmga002.fm.intel.com with ESMTP; 26 Jun 2015 06:59:58 -0700 From: Ramalingam C To: intel-gfx@lists.freedesktop.org, daniel.vetter@ffwll.ch, chris@chris-wilson.co.uk, rodrigo.vivi@intel.com Date: Fri, 26 Jun 2015 19:21:49 +0530 Message-Id: <1435326722-24633-6-git-send-email-ramalingam.c@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1435326722-24633-1-git-send-email-ramalingam.c@intel.com> References: <1435326722-24633-1-git-send-email-ramalingam.c@intel.com> Cc: paulo.r.zanoni@intel.com Subject: [Intel-gfx] [RFC PATCH 05/18] drm/i915: Adjusting the pclk for dual link and burst mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP dsi_clk is calculated for the clock of passed drm_display_mode and pclk is adjusted considering dual link and the burst mode. This change is required to make the drrs to co-exist with dual link and Burst mode. Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/intel_dsi_pll.c | 77 ++++++++++++++++++++++++++++++---- 1 file changed, 68 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index c58eb02..ce5949f 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -128,13 +128,11 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode, #else -/* Get DSI clock from pixel clock */ -static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) +static u32 intel_get_bits_per_pixel(struct intel_dsi *intel_dsi) { - u32 dsi_clk_khz; u32 bpp; - switch (pixel_format) { + switch (intel_dsi->pixel_format) { default: case VID_MODE_FORMAT_RGB888: case VID_MODE_FORMAT_RGB666_LOOSE: @@ -147,10 +145,70 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) bpp = 16; break; } + return bpp; +} + +void adjust_pclk_for_dual_link(struct intel_dsi *intel_dsi, + struct drm_display_mode *mode, u32 *pclk) +{ + /* In dual link mode each port needs half of pixel clock */ + *pclk = *pclk / 2; + + /* + * If pixel_overlap needed by panel, we need to increase the pixel + * clock for extra pixels. + */ + if (intel_dsi->dual_link & DSI_DUAL_LINK_FRONT_BACK) + *pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * + mode->vrefresh, 1000); +} + +void adjust_pclk_for_burst_mode(u32 *pclk, u16 burst_mode_ratio) +{ + *pclk = DIV_ROUND_UP(*pclk * burst_mode_ratio, 100); +} + + +/* To recalculate the pclk considering dual link and Burst mode */ +static u32 intel_drrs_calc_pclk(struct intel_dsi *intel_dsi, + struct drm_display_mode *mode) +{ + u32 pclk; + int pkt_pixel_size; /* in bits */ - /* DSI data rate = pixel clock * bits per pixel / lane count - pixel clock is converted from KHz to Hz */ - dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); + pclk = mode->clock; + + pkt_pixel_size = intel_get_bits_per_pixel(intel_dsi); + + /* In dual link mode each port needs half of pixel clock */ + if (intel_dsi->dual_link) + adjust_pclk_for_dual_link(intel_dsi, mode, &pclk); + + /* Retaining the same Burst mode ratio for DRRS. Need to be tested */ + if (intel_dsi->burst_mode_ratio > 100) + adjust_pclk_for_burst_mode(&pclk, intel_dsi->burst_mode_ratio); + + DRM_DEBUG_KMS("mode->clock : %d, pclk : %d\n", mode->clock, pclk); + return pclk; +} + +/* Get DSI clock from pixel clock */ +static u32 dsi_clk_from_pclk(struct intel_dsi *intel_dsi, + struct drm_display_mode *mode) +{ + u32 dsi_clk_khz; + u32 bpp; + u32 pclk; + + bpp = intel_get_bits_per_pixel(intel_dsi); + + pclk = intel_drrs_calc_pclk(intel_dsi, mode); + + /* + * DSI data rate = pixel clock * bits per pixel / lane count + * pixel clock is converted from KHz to Hz + */ + dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, intel_dsi->lane_count); return dsi_clk_khz; } @@ -205,12 +263,13 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct intel_connector *intel_connector = intel_dsi->attached_connector; int ret; struct dsi_mnp dsi_mnp; u32 dsi_clk; - dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, - intel_dsi->lane_count); + dsi_clk = dsi_clk_from_pclk(intel_dsi, + intel_connector->panel.fixed_mode); ret = dsi_calc_mnp(dsi_clk, &dsi_mnp); if (ret) {