From patchwork Fri Jun 26 13:51:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 6681181 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 15F9FC05AC for ; Fri, 26 Jun 2015 14:00:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 32A44204A7 for ; Fri, 26 Jun 2015 14:00:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3D3C12049C for ; Fri, 26 Jun 2015 14:00:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A8A16EDC7; Fri, 26 Jun 2015 07:00:13 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 504DF6EDCC for ; Fri, 26 Jun 2015 07:00:12 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 26 Jun 2015 07:00:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,685,1427785200"; d="scan'208";a="750978336" Received: from ramaling-desktop.iind.intel.com ([10.223.26.95]) by fmsmga002.fm.intel.com with ESMTP; 26 Jun 2015 07:00:08 -0700 From: Ramalingam C To: intel-gfx@lists.freedesktop.org, daniel.vetter@ffwll.ch, chris@chris-wilson.co.uk, rodrigo.vivi@intel.com Date: Fri, 26 Jun 2015 19:21:52 +0530 Message-Id: <1435326722-24633-9-git-send-email-ramalingam.c@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1435326722-24633-1-git-send-email-ramalingam.c@intel.com> References: <1435326722-24633-1-git-send-email-ramalingam.c@intel.com> Cc: paulo.r.zanoni@intel.com Subject: [Intel-gfx] [RFC PATCH 08/18] drm/i915: VLV eDP DRRS methods X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP VLV related ePD drrs functions are implemented and registered with generic eDP drrs module. This will provide the platform specific services to generic ePD drrs stack, like program the pll registers for DRRS functionality. Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/intel_edp_drrs.c | 72 +++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_edp_drrs.c b/drivers/gpu/drm/i915/intel_edp_drrs.c index 606271b..8968e4c 100644 --- a/drivers/gpu/drm/i915/intel_edp_drrs.c +++ b/drivers/gpu/drm/i915/intel_edp_drrs.c @@ -20,6 +20,71 @@ #include "i915_drv.h" +/* + * VLV eDP DRRS Support + */ + +static int vlv_edp_drrs_init(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + + if (dev_priv->psr.enabled) { + DRM_ERROR("eDP DRRS is disabled as PSR is enabled already\n"); + return -EINVAL; + } + return 0; +} + +static void vlv_edp_drrs_exit(struct intel_encoder *encoder) +{ +} + +static int vlv_edp_set_drrs_state(struct intel_encoder *encoder, + enum drrs_refresh_rate_type target_rr_type) +{ + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); + u32 reg, val; + + if (!crtc) + return -EINVAL; + + reg = PIPECONF(crtc->config->cpu_transcoder); + val = I915_READ(reg); + + switch (target_rr_type) { + case DRRS_HIGH_RR: + if (IS_VALLEYVIEW(dev)) + val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; + break; + case DRRS_LOW_RR: + if (IS_VALLEYVIEW(dev)) + val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; + break; + default: + DRM_ERROR("invalid refresh rate type\n"); + return -EINVAL; + } + + I915_WRITE(reg, val); + return 0; +} + +struct edp_drrs_platform_ops vlv_edp_drrs_ops = { + .init = vlv_edp_drrs_init, + .exit = vlv_edp_drrs_exit, + .set_drrs_state = vlv_edp_set_drrs_state, +}; + +struct edp_drrs_platform_ops *get_vlv_edp_drrs_ops(void) +{ + return &vlv_edp_drrs_ops; +} + +/* + * Generic eDP DRRS implementation + */ void intel_edp_set_drrs_state(struct i915_drrs *drrs) { struct intel_encoder *intel_encoder = drrs->connector->encoder; @@ -37,6 +102,13 @@ int intel_edp_drrs_init(struct i915_drrs *drrs, struct drm_display_mode *downclock_mode; int ret = -EINVAL; + if (IS_VALLEYVIEW(intel_encoder->base.dev)) + + /* VLV and CHV */ + intel_dp->drrs_ops = get_vlv_edp_drrs_ops(); + else + intel_dp->drrs_ops = NULL; + if (!intel_dp->drrs_ops || !intel_dp->drrs_ops->set_drrs_state) { DRM_ERROR("Required platform ops are NULL\n");